MC9S12DG128MPVE Datasheet, PDF (82/128 Pages) Freescale Semiconductor, Inc – Device User Guide

MC9S12DT128B Device User G^Fu^rid^ee^e—^sV^c0^a1.^l0^e9 ^{Semiconductor, Inc.}
Section 22 Printed Circuit Board Layout Proposal
Table 22-1 Suggested External Component Values
Component
C1
C2
C3
C4
C5
C6
C7
C8
C9 / C_S
C10 / C_P
C11 / C_DC
R1 / R
R2 / R_B
R3 / R_S
Q1
Purpose
VDD1 filter cap
VDD2 filter cap
VDDA filter cap
VDDR filter cap
VDDPLL filter cap
VDDX filter cap
OSC load cap
OSC load cap
PLL loop filter cap
PLL loop filter cap
DC cutoff cap
PLL loop filter res
Quartz
Type
ceramic X7R
ceramic X7R
ceramic X7R
X7R/tantalum
ceramic X7R
X7R/tantalum
Value
100 … 220nF
100 … 220nF
100nF
>= 100nF
100nF
>= 100nF
See PLL specification chapter
Colpitts mode only, if recommended by
quartz manufacturer
See PLL Specification chapter
Pierce mode only
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
• Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1 – C6).
• Central point of the ground star should be the VSSR pin.
• Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.
• VSSPLL must be directly connected to VSSR.
• Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,
C8, C11 and Q1 as small as possible.
• Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the
connection area to the MCU.
• Central power input should be fed in at the VDDA/VSSA pins.
For More Information On This Product,
Go to: www.freescale.com