MC33912_10 Datasheet, PDF (89/94 Pages) Freescale Semiconductor, Inc – LIN System Basis Chip with DC Motor Pre-driver and Current Sense

MC33912BAC / MC34912BAC
FUNCTIONAL DEVICE OPERATIONS
Interrupt Mask Register - IMR
This register allows masking of some of the interrupt
sources. The respective flags within the Interrupt Source
Register (ISR) will continue to work but will not generate
interrupts to the MCU. The 5.0 V Regulator over-temperature
prewarning interrupt and Under-Voltage (VSUV) interrupts
can not be masked and will always cause an interrupt.
Writing to the IMR will return the ISR.
Table 60. Interrupt Mask Register - $E
C3
C2
C1
C0
Write
HSM
LSM
LINM
VMM
Reset
Value
1
1
1
1
Reset
Condition
POR
HSM - High Side Interrupt Mask
This write-only bit enables/disables interrupts generated in
the high side block.
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
LSM - Low Side Interrupt Mask
This write-only bit enables/disables interrupts generated in
the low side block.
1 = LS Interrupts Enabled
0 = LS Interrupts Disabled
LINM - LIN Interrupts Mask
This write-only bit enables/disables interrupts generated in
the LIN block.
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
VMM - Voltage Monitor Interrupt Mask
This write-only bit enables/disables interrupts generated in
the Voltage Monitor block. The only maskable interrupt in the
Voltage Monitor Block is the V_SUP over-voltage interrupt.
1 = Interrupts Enabled
0 = Interrupts Disabled
Interrupt Source Register - ISR
This register allows the MCU to determine the source of
the last interrupt or wake-up respectively. A read of the
register acknowledges the interrupt and leads IRQ pin to
high, in case there are no other pending interrupts. If there
are pending interrupts, IRQ will be driven high for 10 µs and
then be driven low again.
This register is also returned when writing to the Interrupt
Mask Register (IMR).
Table 61. Interrupt Source Register - $E/$F
S3
S2
S1
S0
Read
ISR3
ISR2
ISR1
ISR0
ISRx - Interrupt Source Register
These read-only bits indicate the interrupt source following
Table 62. If no interrupt is pending then all bits are 0.
In case more than one interrupt is pending, the interrupt
sources are handled sequentially multiplex.
Table 62. Interrupt Sources
Interrupt Source
ISR3 ISR2 ISR1 ISR0
none maskable
maskable
0
0
0
0
no interrupt
no interrupt
0
0
0
1
Lx Wake-up from Stop mode-
0
0
1
0
-
0
0
1
1
-
HS Interrupt (Over-temperature)
LS Interrupt (Over-temperature)
0
1
0
0
LIN Interrupt (RXSHORT, TXDOM, LIN OT, LIN
OC) or LIN Wake-up
0
1
0
1
Voltage Monitor Interrupt
(Low Voltage and VDD over-temperature)
Voltage Monitor Interrupt
(High Voltage)
0
1
1
0
-
Forced Wake-up
Priority
none
highest
lowest
Analog Integrated Circuit Device Data
Freescale Semiconductor
33912
89