MC33912_10 Datasheet, PDF (87/94 Pages) Freescale Semiconductor, Inc – LIN System Basis Chip with DC Motor Pre-driver and Current Sense

MC33912BAC / MC34912BAC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Timing Control Register - TIMCR
This register is a double purpose register which allows to
configure the watchdog and the cyclic sense periods. Writing
to the Timing Control Register (TIMCR) will also return the
Watchdog Status Register (WDSR).
Table 53. Timing Control Register - $A
C3
C2
C1
C0
Write
CS/WD
WD2
CYST2
WD1
CYST1
WD0
CYST0
Reset
Value
-
0
0
0
Reset
Condition
-
POR
CS/WD - Cyclic Sense or Watchdog prescaler select
This write-only bit selects which prescaler is being written
to, the Cyclic Sense prescaler or the Watchdog prescaler.
1 = Cyclic Sense Prescaler selected
0 = Watchdog Prescaler select
WDx - Watchdog Prescaler
This write-only bits selects the divider for the watchdog
prescaler and therefore selects the watchdog period in
accordance with Table 54. This configuration is valid only if
windowing watchdog is active.
Table 54. Watchdog Prescaler
WD2 WD1 WD0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Prescaler Divider
1
2
4
6
8
10
12
14
CYSTx - Cyclic Sense Period Prescaler Select
This write-only bits selects the interval for the wake-up
cyclic sensing together with the bit CYSX8 in the
Configuration Register (CFR) (see Configuration Register -
CFR).
This option is only active if one of the high side switches is
enabled when entering in Stop or Sleep mode. Otherwise a
timed wake-up is performed after the period shown in
Table 55.
Table 55. Cyclic Sense Interval
CYSX8⁽¹³²⁾ CYST2 CYST1 CYST0
Interval
X
0
0
0
No cyclic sense
0
0
0
1
20 ms
0
0
1
0
40 ms
0
0
1
1
60 ms
0
1
0
0
80 ms
0
1
0
1
100 ms
0
1
1
0
120 ms
0
1
1
1
140 ms
1
0
0
1
160 ms
1
0
1
0
320 ms
1
0
1
1
480 ms
1
1
0
0
640 ms
1
1
0
1
800 ms
1
1
1
0
960 ms
1
1
1
1
1120 ms
Notes
132. bit CYSX8 is located in Configuration Register (CFR)
Watchdog Status Register - WDSR
This register returns the Watchdog status information and
is also returned when writing to the TIMCR.
Table 56. Watchdog Status Register - $A/$B
S3
S2
S1
S0
Read WDTO WDERR WDOFF WDWO
WDTO - Watchdog Timeout
This read-only bit signals the last reset was caused by
either a watchdog timeout or by an attempt to clear the
Watchdog within the window closed.
Any access to this register or the Timing Control Register
(TIMCR) will clear the WDTO bit.
1 = Last reset caused by watchdog timeout
0 = None
Analog Integrated Circuit Device Data
Freescale Semiconductor
33912
87