MC68HC705C8ACFNE Datasheet, PDF (87/222 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O)
Port C
7.5.3 Port C Logic
Figure 7-9 shows port C I/O logic.
READ $0006
WRITE $0006
RESET
DATA DIRECTION
REGISTER C
BIT DDRCx
WRITE $0002
PORT C DATA
REGISTER
PCx
BIT PCx
READ $0002
Figure 7-9. Port C I/O Logic
When a port C pin is programmed as an output, reading the port bit reads
the value of the data latch and not the voltage on the pin. When a port C
pin is programmed as an input, reading the port bit reads the voltage
level on the pin. The data latch can always be written, regardless of the
state of its DDRC bit. Table 7-3 summarizes the operation of the port C
pins.
Table 7-3. Port C Pin Functions
DDRC Bit I/O Pin Mode
Accesses to DDRC
Read/Write
0
Input, Hi-Z⁽¹⁾
DDRC7–DDRC0
1
Output
DDRC7–DDRC0
1. Hi-Z = high impedance
2. Writing affects data register but does not affect input.
Accesses to PORTC
Read
Write
Pin
PC7–PC0⁽²⁾
PC7–PC0 PC7–PC0
NOTE:
To avoid excessive current draw, tie all unused input pins to V_DD or V_SS
or change I/O pins to outputs by writing to DDRC in user code as early
as possible.
MC68HC705C8A — Rev. 3
MOTOROLA
Parallel Input/Output (I/O)
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Technical Data