MC68HC705C8ACFNE Datasheet, PDF (146/222 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
MASTER/SLAVE
MCU 1
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
0
I/O ¹
PORT ₂
3
MASTER/SLAVE
MCU 2
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
0
1 _I/O
2 ^PORT
3
SLAVE MCU 2
SLAVE MCU 1
SLAVE MCU 0
Figure 11-5. Two Master/Slaves and Three Slaves Block Diagram
11.6 Serial Clock Polarity and Phase
To accommodate the different serial communication requirements of
peripheral devices, software can change the phase and polarity of the
SPI serial clock. The clock polarity bit (CPOL) and the clock phase bit
(CPHA), both in the SPCR, control the timing relationship between the
serial clock and the transmitted data. Figure 11-6 shows how the CPOL
and CPHA bits affect the clock/data timing.
CPHA CPOL
0
0
SS
SCK (A)
1
0
SCK (B)
0
1
SCK (C)
1
1
SCK (D)
SDO/SDI
CAPTURE STROBE
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
Figure 11-6. SPI Clock/Data Timing
Technical Data
146
Serial Peripheral Interface (SPI)
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MC68HC705C8A — Rev. 3