MC68HC705C8ACFNE Datasheet, PDF (57/222 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Interrupts
Interrupt Processing
4.4 Interrupt Processing
The CPU takes these actions to begin servicing an interrupt:
1. Stores the CPU registers on the stack in the order shown in
Figure 4-4
2. Sets the I bit in the CCR to prevent further interrupts
3. Loads the program counter with the contents of the appropriate
interrupt vector locations as shown in Table 4-1.
Table 4-1. Reset/Interrupt Vector Addresses
Function Source
Local
Mask
Global
Mask
Priority
(1 = Highest)
Vector Address
Power-on
Reset
logic
None None
1
$1FFE–$1FFF
RESET pin
Software
interrupt
(SWI)
User code
None
None
Same priority
as any
instruction
$1FFC–$1FFD
External
interrupt
IRQ pin
Port B pins
None
I bit
2
$1FFA–$1FFB
ICF bit
ICIE bit
Timer
interrupts
OCF bit
OCIE bit
I bit
TOF bit TOIE bit
3
$1FF8–$1FF9
TDRE bit
TC bit
TCIE bit
SCI
interrupts
RDRF bit
RIE bit
I bit
OR bit
4
$1FF6–$1FF7
IDLE bit ILIE bit
SPI
interrupts
SPIF bit
MODF bit
SPIE
I bit
5
$1FF4–$1FF5
The return-from-interrupt (RTI) instruction causes the CPU to recover
the CPU registers from the stack as shown in Figure 4-4.
MC68HC705C8A — Rev. 3
MOTOROLA
Interrupts
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Technical Data