MC68HC705C8ACFNE Datasheet, PDF (86/222 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O)
7.5.2 Data Direction Register C
The contents of data direction register C (DDRC) shown in Figure 7-8
determine whether each port C pin is an input or an output. Writing a
logic 1 to a DDRC bit enables the output buffer for the associated port C
pin; a logic 0 disables the output buffer. A reset clears all DDRC bits,
configuring all port C pins as inputs.
Address: $0006
Bit 7
6
5
4
3
2
1
Read:
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1
Write:
Reset: 0
0
0
0
0
0
0
Figure 7-8. Data Direction Register C (DDRC)
Bit 0
DDRC0
0
DDRC7–DDRC0 — Port C Data Direction Bits
These read/write bits control port C data direction. Reset clears bits
DDRC7–DDRC0.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE: Avoid glitches on port C pins by writing to the port C data register before
changing DDRC bits from logic 0 to logic 1.
Technical Data
86
Parallel Input/Output (I/O)
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MC68HC705C8A — Rev. 3