MC68HC705C8ACFNE Datasheet, PDF (65/222 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Resets
Reset Sources
CME — Clock Monitor Enable Bit
This read/write bit enables the clock monitor. The clock monitor sets
the COPF bit and generates a reset if it detects an absent internal
clock for a period of from 5 µs to 100 µs. CME is readable and writable
at any time. Reset clears the CME bit.
1 = Clock monitor enabled
0 = Clock monitor disabled
NOTE: Do not enable the clock monitor in applications with an internal clock
frequency of 200 kHz or less.
If the clock monitor detects a slow clock, it drives the bidirectional
RESET pin low for four clock cycles. If the clock monitor detects an
absent clock, it drives the RESET pin low until the clock recovers.
PCOPE — Programmable COP Enable Bit
This read/write bit enables the programmable COP watchdog.
PCOPE is readable at any time but can be written only once after
reset. Reset clears the PCOPE bit.
1 = Programmable COP watchdog enabled
0 = Programmable COP watchdog disabled
NOTE:
Programming the non-programmable COP enable bit (NCOPE) in mask
option register 2 (MOR2) to logic 1 enables the non-programmable COP
watchdog. Setting the PCOPE bit while the NCOPE bit is programmed
to logic 1 enables both COP watchdogs to operate at the same time.
(See 9.5.3 Mask Option Register 2.)
CM1 and CM0 — COP Mode Bits
These read/write bits select the timeout period of the programmable
COP watchdog. (See Table 5-1.) CM1 and CM0 can be read anytime
but can be written only once. They can be cleared only by reset.
Bits 7–5 — Unused
Bits 7–5 always read as logic 0s. Reset clears bits 7–5.
MC68HC705C8A — Rev. 3
MOTOROLA
Resets
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Technical Data