MC68HC705C8ACFNE Datasheet, PDF (75/222 Pages) Freescale Semiconductor, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Low-Power Modes
Data-Retention Mode
6.4.1 Programmable COP Watchdog in Wait Mode
The programmable COP watchdog is active during wait mode. Software
must periodically bring the MCU out of wait mode to clear the
programmable COP watchdog.
6.4.2 Non-Programmable COP Watchdog in Wait Mode
The non-programmable COP watchdog is active during wait mode.
Software must periodically bring the MCU out of wait mode to clear the
non-programmable COP watchdog.
6.5 Data-Retention Mode
In data-retention mode, the MCU retains random-access memory (RAM)
contents and CPU register contents at V_DD voltages as low as 2.0 Vdc.
The data-retention feature allows the MCU to remain in a low
power-consumption state during which it retains data, but the CPU
cannot execute instructions.
To put the MCU in data-retention mode:
1. Drive the RESET pin to logic 0.
2. Lower V_DD voltage. The RESET pin must remain low continuously
during data-retention mode.
To take the MCU out of data-retention mode:
1. Return V_DD to normal operating voltage.
2. Return the RESET pin to logic 1.
MC68HC705C8A — Rev. 3
MOTOROLA
Low-Power Modes
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Technical Data