MC68L300 Datasheet, PDF (8/32 Pages) Freescale Semiconductor, Inc – 16.78 MHz Electrical Characteristics

Freescale Semiconductor, Inc.
Table 6 16.78 MHz AC Timing (Continued)
(V_DD and V_DDSYN = 3.0 to 3.6Vdc, V_SS = 0 Vdc, T_A = T_L to T_H)¹
Num
Characteristic
Symbol Min
Max Unit
46A R/W Width Asserted (Fast Write or Read Cycle)
47A
Asynchronous Input Setup Time
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
t_RWAS
90
t_AIST
5
— ns
— ns
47B Asynchronous Input Hold Time
48 DSACK[1:0] Asserted to BERR, HALT Asserted⁹
53 Data Out Hold from Clock High
54 Clock High to Data Out High Impedance
55 R/W Asserted to Data Bus Impedance Change
70 Clock Low to Data Bus Driven (Show Cycle)
71 Data Setup Time to Clock Low (Show Cycle)
72 Data Hold from Clock Low (Show Cycle)
73 BKPT Input Setup Time
74 BKPT Input Hold Time
75 Mode Select Setup Time
76 Mode Select Hold Time
77 RESET Assertion Time¹⁰
78 RESET Rise Time^11,12
t_AIHT
15
t_DABA
—
t_DOCH
0
t_CHDH
—
t_RADC
40
t_SCLDD
0
t_SCLDS
15
t_SCLDH
10
t_BKST
15
t_BKHT
10
t_MSS
20
t_MSH
0
t_RSTA
4
t_RSTR
—
— ns
30 ns
— ns
28 ns
— ns
29 ns
— ns
— ns
— ns
— ns
— t_cyc
— ns
— t_cyc
10 t_cyc
NOTES:
1. All AC timing is shown with respect to 20% V_DD and 70% V_DD levels unless otherwise noted.
2. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum
allowable t_Xcyc period is reduced when the duty cycle of the external clock varies. The relationship between ex-
ternal clock input duty cycle and minimum t_Xcyc is expressed:
Minimum t_Xcyc period = minimum t_XCHL / (50% – external clock input duty cycle tolerance).
3. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative
loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall outside
the limits shown in specification 9.
4. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a
heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification be-
tween multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles.
5. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast
cycle reads. The user is free to use either hold time.
6. Maximum value is equal to (t_cyc / 2) + 25 ns.
7. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data setup
time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ignored. The data
must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must
satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle.
8. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all cycles
of the current operand transfer are complete.
9. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time (specification
47A).
10. After external RESET negation is detected, a short transition period (approximately 2) t_cyc elapses, then the SIM
drives RESET low for 512 t_cyc.
11. External assertion of the RESET input can overlap internally-generated resets. To insure that an external reset
is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles.
12. External logic must pull RESET high during this period in order for normal MCU operation to begin.
8
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MC68L300EC16/D