MC68L300 Datasheet, PDF (19/32 Pages) Freescale Semiconductor, Inc – 16.78 MHz Electrical Characteristics

Freescale Semiconductor, Inc.
Table 9 QSPI Timing
(V_DD and V_DDSYN = 3.0 to 3.6Vdc, V_SS = 0 Vdc, T_A = T_L to T_{H , 100 pF load on all QSPI pins)}¹
Num
Function
Symbol
Min
Max
Unit
Operating Frequency
1 Master
Slave
Cycle Time
2 Master
Slave
Enable Lead Time
3 Master
Slave
Enable Lag Time
4 Master
Slave
Clock (SCK) High or Low Time
5 Master
Slave²
Sequential Transfer Delay
6 Master
Slave (Does Not Require Deselect)
Data Setup Time (Inputs)
7 Master
Slave
f_op
DC
1/4
DC
1/4
t_qcyc
4
510
4
—
t_lead
2
128
2
—
t_lag
—
1/2
2
—
t_sw
2 t_cyc – 60 255 t_cyc
2 t_cyc – n
—
t_td
17
8192
13
—
t_su
30
—
20
—
f_sys
f_sys
t_cyc
t_cyc
t_cyc
t_cyc
SCK
t_cyc
ns
ns
t_cyc
t_cyc
ns
ns
Data Hold Time (Inputs)
8 Master
Slave
t_hi
0
—
ns
20
—
ns
9 Slave Access Time
10 Slave MISO Disable Time
Data Valid (after SCK Edge)
11 Master
Slave
t_a
—
1
t_cyc
t_dis
—
2
t_cyc
t_v
—
50
ns
—
50
ns
Data Hold Time (Outputs)
12 Master
Slave
t_ho
0
—
ns
0
—
ns
Rise Time
13 Input
Output
t_ri
—
2
µs
t_ro
—
30
ns
Fall Time
14 Input
Output
t_fi
—
2
µs
t_fo
—
30
ns
NOTES:
1. All AC timing is shown with respect to 20% V_DD and 70% V_DD levels unless otherwise noted.
2. For high time, n = External SCK rise time; for low time, n = External SCK fall time.
MC68L300EC16/D
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Go to: www.freescale.com
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