MC68L300 Datasheet, PDF (24/32 Pages) Freescale Semiconductor, Inc – 16.78 MHz Electrical Characteristics

PHI1^*
PAEN
EXT PIN (PAI)
Freescale Semiconductor, Inc.
A
B
PACNT
$FF
$00
PAIF
PAOVF
NOTE: 1.
2.
3.
4.
5.
A = PAI signal after the synchronizer
B = “A” after the digital filter
*PHI1 _{is the same frequency as system clock; however, it does not have the same timing.}
The external leading edge causes the pulse accumulator to increment and the PAIF flag to be set.
The counter transition from $FF to $00 causes the PAOVF flag to be set.
Figure 22 Pulse Accumulator — Event Counting Mode (Leading Edge)
24
For More Information On This Product,
Go to: www.freescale.com
MC68L300EC16/D