MC68L300 Datasheet, PDF (7/32 Pages) Freescale Semiconductor, Inc – 16.78 MHz Electrical Characteristics

Freescale Semiconductor, Inc.
Table 6 16.78 MHz AC Timing
(V_DD and V_DDSYN = 3.0 to 3.6Vdc, V_SS = 0 Vdc, T_A = T_L to T_H)¹
Num
Characteristic
F1 Frequency of Operation
1 Clock Period
1A ECLK Period
1B External Clock Input Period²
2, 3 Clock Pulse Width
2A, 3A ECLK Pulse Width
2B, 3B External Clock Input High/Low Time²
4, 5 CLKOUT Rise and Fall Time
4A, 5A Rise and Fall Time (All outputs except CLKOUT)
4B, 5B External Clock Input Rise and Fall Time
6 Clock High to ADDR, FC, RMC, SIZ Valid
7 Clock High to ADDR, Data, FC, RMC,SIZ High Impedance
8 Clock High to ADDR, FC, RMC, SIZ Invalid
9 Clock Low to AS, DS, CS Asserted
9A AS to DS or CS Asserted (Read)³
9C Clock Low to IFETCH, IPIPE Asserted
11 ADDR, FC, RMC, SIZ Valid to AS, CS, (and DS Read) Asserted
12 Clock Low to AS, DS, CS Negated
12A Clock Low to IFETCH, IPIPE Negated
13 AS, DS, CS Negated to ADDR, FC, SIZ Invalid (Address Hold)
14 AS, CS (and DS Read) Width Asserted
14A DS, CS Width Asserted (Write)
14B AS, CS (and DS Read) Width Asserted (Fast Cycle)
15 AS, DS, CS Width Negated⁴
16 Clock High to AS, DS, R/W High Impedance
17 AS, DS, CS Negated to R/W High
18 Clock High to R/W High
20 Clock High to R/W Low
21 R/W High to AS, CS Asserted
22 R/W Low to DS, CS Asserted (Write)
23 Clock High to Data Out Valid
24 Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle)
25 DS, CS Negated to Data Out Invalid (Data Out Hold)
26 Data Out Valid to DS, CS Asserted (Write)
27 Data In Valid to Clock Low (Data Setup)
27A Late BERR, HALT Asserted to Clock Low (Setup Time)
28 AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
29 DS, CS Negated to Data In Invalid (Data In Hold)⁵
29A DS, CS Negated to Data In High Impedance^{5, 6}
30 CLKOUT Low to Data In Invalid (Fast Cycle Hold)⁵
30A CLKOUT Low to Data In High Impedance⁵
31 DSACK[1:0] Asserted to Data In Valid⁷
33 Clock Low to BG Asserted/Negated
35 BR Asserted to BG Asserted (RMC not Asserted)⁸
37 BGACK Asserted to BG Negated
39 BG Width Negated
39A BG Width Asserted
46 R/W Width Asserted (Write or Read)
Symbol
f_sys
t_cyc
t_Ecyc
t_Xcyc
t_CW
t_ECW
t_XCHL
t_Crf
t_rf
t_XCrf
t_CHAV
t_CHAZx
t_CHAZn
t_CLSA
t_STSA
t_CLIA
t_AVSA
t_CLSN
t_CLIN
t_SNAI
t_SWA
t_SWAW
t_SWDW
t_SN
t_CHSZ
t_SNRN
t_CHRH
t_CHRL
t_RAAA
t_RASA
t_CHDO
t_DVASN
t_SNDOI
t_DVSA
t_DICL
t_BELCL
t_SNDN
t_SNDI
t_SHDI
t_CLDI
t_CLDH
t_DADI
t_CLBAN
t_BRAGA
t_GAGN
t_GH
t_GA
t_RWA
Min
—
59.6
476
59.6
24
236
29.8
—
—
—
0
0
0
0
–15
2
15
2
2
15
100
45
40
40
—
15
0
0
15
70
—
15
15
15
5
20
0
0
—
10
—
—
—
1
1
2
1
150
Max Unit
16.78 MHz
— ns
— ns
— ns
— ns
— ns
— ns
7 ns
8 ns
4 ns
29 ns
59 ns
— ns
25 ns
15 ns
22 ns
— ns
29 ns
29 ns
— ns
— ns
— ns
— ns
— ns
59 ns
— ns
29 ns
29 ns
— ns
— ns
29 ns
— ns
— ns
— ns
— ns
— ns
80 ns
— ns
55 ns
— ns
90 ns
50 ns
29 ns
— t_cyc
2 t_cyc
— t_cyc
— t_cyc
— ns
MC68L300EC16/D
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