MC68L300 Datasheet, PDF (15/32 Pages) Freescale Semiconductor, Inc – 16.78 MHz Electrical Characteristics

CLKOUT
ADDR[23:0]
DATA[15:0]
Freescale Semiconductor, Inc.
A0
A5
A5
A2
A3
A0
AS
47A
47A
BR
BG
BGACK
35
33
37
47A
33
Figure 9 Bus Arbitration Timing Diagram — Idle Bus Case
68300 BUS ARB TIM IDLE
CLKOUT
S0
S41
S42
S43
S0
S1
S2
6
8
ADDR[23:0]
18
R/W
20
AS
9
12
15
DS
DATA[15:0]
BKPT
70
73
74
SHOW CYCLE
71
72
START OF EXTERNAL CYCLE
NOTE:
Show cycles can stretch during clock phase S42 when bus accesses take longer than two cycles due to IMB module
wait-state insertion.
Figure 10 Show Cycle Timing Diagram
68300 SHW CYC TIM
MC68L300EC16/D
For More Information On This Product,
Go to: www.freescale.com
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