MC68L300 Datasheet, PDF (18/32 Pages) Freescale Semiconductor, Inc – 16.78 MHz Electrical Characteristics

Freescale Semiconductor, Inc.
Table 8 ECLK Bus Timing
(V_DD and V_DDSYN = 3.0 to 3.6Vdc, V_SS = 0 Vdc, T_A = T_L to T_H)¹
Num
Characteristic
Symbol Min
Max
E1 ECLK Low to Address Valid²
t_EAD
—
60
E2 ECLK Low to Address Hold
t_EAH
15
—
E3 ECLK Low to CS Valid (CS Delay)
E4 ECLK Low to CS Hold
t_ECSD
—
150
t_ECSH
15
—
E5 CS Negated Width
t_ECSN
30
—
E6 Read Data Setup Time
E7 Read Data Hold Time
t_EDSR
30
—
t_EDHR
5
—
E8 ECLK Low to Data High Impedance
t_EDHZ
—
60
E9 CS Negated to Data Hold (Read)
t_ECDH
0
—
E10 CS Negated to Data High Impedance
t_ECDZ
—
1
E11 ECLK Low to Data Valid (Write)
t_EDDW
—
2
E12 ECLK Low to Data Hold (Write)
E13 Address Access Time (Read)³
E14 Chip-Select Access Time (Read)⁴
t_EDHW
15
—
t_EACC
386
—
t_EACS
296
—
E15 Address Setup Time
t_EAS
1/2
—
NOTES:
1. All AC timing is shown with respect to 20% V_DD and 70% V_DD levels unless otherwise noted.
2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = t_Ecyc – t_EAD – t_EDSR.
4. Chip select access time = t_Ecyc – t_ECSD – t_EDSR.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t_cyc
t_cyc
ns
ns
ns
t_cyc
CLKOUT
ECLK
R/W
ADDR[23:0]
CS
DATA[15:0]
DATA[15:0]
2A
3A
1A
E1
E3
E15
E11
E2
E14
E6
E13
WRITE
Figure 15 ECLK Timing Diagram
E4
E5
READ
E7
E9
WRITE
E8
E10
E12
68300 E CYCLE TIM
18
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MC68L300EC16/D