MC68L300 Datasheet, PDF (6/32 Pages) Freescale Semiconductor, Inc – 16.78 MHz Electrical Characteristics

Freescale Semiconductor, Inc.
NOTES:
1. Applies to:
QSM pins
IRQ[7:1], RESET, EXTAL, TSC, RMC, BKPT/DSCLK, IFETCH/DSI
2. Input-Only Pins: TSC, BKPT/DSCLK, RXD
Output-Only Pins: CSBOOT, BG/CS, CLKOUT, FREEZE/QUOT, IPIPE/DSO
Input/Output Pins:
Group 1: DATA[15:0], IFETCH/DSI
Group 2: ADDR[23:19]/CS[10:6], FC[2:0]/CS[5:3], DSACK[1:0], AVEC, RMC, DS, AS, SIZ[1:0]
IRQ[7:1], MODCLK, ADDR[18:0], R/W, BERR, BR/CS0, BGACK/CS2, PCS[3:1], PCS0/SS, TXD
Group 3: HALT, RESET
Group 4: MISO, MOSI, SCK
3. Does not apply to HALT and RESET because they are open drain pins.
Does not apply to Port QS[7:0] (TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO) in wired-OR mode.
4. Current measured at maximum system clock frequency.
5. Total operating current is the sum of the appropriate V_DD supply and V_DDSYN supply current.
6. When V_SB is more than 0.3V greater than V_DD, current flows between the V_STBY and V_DD pins, which causes
standby current to increase toward the maximum condition specification. System noise on the V_DD and V_STBY
pin can contribute to this condition.
7. The SRAM module will not switch into standby mode as long as V_SB does not exceed V_DD by more than 0.5
volts. The SRAM array cannot be accessed while the module is in standby mode.
8. Power dissipation measured at specified system clock frequency. Power dissipation can be calculated using the
expression:
P_D = 3.6V (I_DDSYN + I_DD)
9. Input capacitance is periodically sampled rather than 100% tested.
6
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MC68L300EC16/D