MC68L300 Datasheet, PDF (17/32 Pages) Freescale Semiconductor, Inc – 16.78 MHz Electrical Characteristics

Freescale Semiconductor, Inc.
Table 7 Background Debugging Mode Timing
(V_DD and V_DDSYN = 3.0 to 3.6Vdc, V_SS = 0 Vdc, T_A = T_L to T_H)¹
Num
Characteristic
Symbol Min
Max Unit
B0 DSI Input Setup Time
B1 DSI Input Hold Time
B2 DSCLK Setup Time
B3 DSCLK Hold Time
B4 DSO Delay Time
B5 DSCLK Cycle Time
B6 CLKOUT Low to FREEZE Asserted/Negated
B7 CLKOUT High to IFETCH High Impedance
B8 CLKOUT High to IFETCH Valid
B9 DSCLK Low Time
t_DSISU
15
t_DSIH
10
t_DSCSU
15
t_DSCH
10
t_DSOD
—
t_DSCCYC
2
t_FRZAN
—
t_IPZ
—
t_IP
—
t_DSCLO
1
—
ns
—
ns
—
ns
—
ns
25
ns
—
t_cyc
50
ns
50
ns
50
ns
—
t_cyc
NOTES:
1. All AC timing is shown with respect to 20% V_DD and 70% V_DD levels unless otherwise noted.
CLKOUT
FREEZE
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
B3
B2
B9
B5
B1
B0
B4
Figure 13 BDM Serial Communication Timing Diagram
68300 BKGD DBM SER COM TIM
CLKOUT
FREEZE
IFETCH/DSI
B6
B7
B6
B8
Figure 14 BDM Freeze Assertion Timing Diagram
68300 BDM FRZ TIM
MC68L300EC16/D
For More Information On This Product,
Go to: www.freescale.com
17