MC33937 Datasheet, PDF (8/48 Pages) Freescale Semiconductor, Inc – Three Phase Field Effect Transistor Pre-driver

ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 8.0 V  V_PWR = V_SUP  40 V-40 C  T_A  135 C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T_A = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUTS
VPWR Supply Voltage Startup Threshold⁽⁹⁾
VSUP Supply Current, V_PWR = V_SUP = 40 V
RST and ENABLE = 5.0 V
No output loads on Gate Drive Pins, No PWM
No output loads on Gate Drive Pins, 20 kHz, 50% Duty Cycle
VPWR Supply Current, V_PWR = V_SUP = 40 V
RST and ENABLE = 5.0 V
No output loads on Gate Drive Pins, No PWM, Outputs initialized
Output Loads = 620 nC per FET, 20 kHz PWM⁽¹⁰⁾
Sleep State Supply Current, RST = 0 V
V_SUP = 40 V
V_PWR = 40 V
Sleep State Output Gate Voltage
IG < 100 µA
Trickle Charge Pump (Bootstrap Voltage)⁽¹⁴⁾
V_SUP = 14 V
Bootstrap Diode Forward Voltage at 10 mA
VDD INTERNAL REGULATOR
V_DD Output Voltage, V_PWR = 8 to 40 V, C = 0.47 µF⁽¹¹⁾
External Load I_{DD_EXT} = 0 to 1.0 mA
Internal V_DD Supply Current, V_DD = 5.5 V, No External Load
VLS REGULATOR
V_{PWR_ST}
–
I_SUP
–
–
I_{PWR_ON}
–
–
I_SUP
–
I_PWR
–
V_GATESS
–
V_Boot
22
V_F
–
6.0
8.0
V
mA
1.0
–
–
10
mA
11
20
–
95
µA
14
30
56
100
V
–
1.3
V
28
32
–
1.2
V
V_DD
V
4.5
–
5.5
I_DD
–
–
12
mA
Peak Output Current, V_PWR = 16 V, V_LS = 10 V
Linear Regulator Output Voltage, I_VLS = 0 to 60 mA,V_PWR > V_LS + 2.0 V⁽¹²⁾
VLS Disable Threshold⁽¹³⁾
I_PEAK
V_LS
V_THVLS
350
600
13.5
15
7.5
8.0
800
mA
17
V
8.5
V
Notes
9. Operation with the Charge Pump is recommended when minimum system voltage could be less than 14 V. V_PWR must exceed this
threshold in order for the Charge Pump and V_DD regulator to startup and drive V_PWR to > 8.0 V. Once V_PWR exceeds 8.0 V, the circuits
will continue to operate even if system voltage drops below 6.0 V.
10. This parameter is guaranteed by design. It is not production tested.
11. Minimum external capacitor for stable V_DD operation is 0.47 µF.
12. Recommended external capacitor for the V_LS regulator is 2.2 µF low ESR at each pin VLS and VLS_CAP.
13. When V_LS is less than this value, the outputs are disabled and HOLDOFF circuits are active. Recovery requires initialization when V_LS
rises above this threshold again. A filter delay of approximately 700 ns on the comparator output eliminates responses to spurious
transients on V_LS.
14. See Figure 11 for typical capability to maintain gate voltage with a 5.0 µA load.
33937A
8
Analog Integrated Circuit Device Data
Freescale Semiconductor