MC33937 Datasheet, PDF (27/48 Pages) Freescale Semiconductor, Inc – Three Phase Field Effect Transistor Pre-driver

FUNCTIONAL INTERNAL BLOCK DESCRIPTION
3x
VLS
VSUP
T-Lim
Desat.
Comp.
VSUP
+
1 ._-4V
Phase
Comp.
VSUP
R
R
HS
Control
High Px_BOOT
-Side
Driver
Px_HS_G
Px_HS_S
LS
Control
Low
-Side
Driver
Px_LS_G
VLS_CAP
Px_LS_S
To Current
Sense Amplif.
Phase x
Output
Phase x Output
Shorted to Ground
(Low-Side
FET Shorted)
Phase
Return
RSense
3x
VLS
V _SUP
T-Lim
Desat.
Comp.
VSUP
+
1._-4V
Phase
Comp.
VSUP
R
R
HS
Control
High Px_BOOT
-Side
Driver
Px_HS_G
Px_HS_S
LS
Control
Low
-Side
Driver
P x_LS_G
V LS_CA P
P x_LS_S
To Current
Sense Amplif.
Phase x Output
Shorted to VSUP
(High-Side
FET Shorted)
Phase x
Output
Phase
Return
RS _{ens e}
Px_HS_G
Px_LS_G
VSUP
tBLANK
Deadtime
tFILT
Correct Phase x Output Voltage
-VD
PHASEx
0.5VSUP
Phase x Output
Voltage Shorted to Ground
Correct
Fault
Phase Error
Desaturation Error
Figure 15. Short to Ground Detection
When switching from Low Side to High Side, the High Side
will be commanded ON after the end of the deadtime. The
deadtime period starts when the Low Side is commanded
OFF. If the voltage at Px_HS_S is less than 1.4V below V_SUP
after the blanking time (t_BLANK) a desaturation fault is
initiated. An additional 1.0 s digital filter is applied from the
initiation of the desaturation fault before it is registered, and
all phase drivers are turned OFF (Px_HS_G clamped to
Px_HS_S and Px_LS_G clamped to Px_LS_S). If the
desaturation fault condition clears before the filter time
expires, the fault is ignored and the filter timer resets.
Valid faults are registered in the fault status register, which
can be retrieved by way of the SPI. Additional SPI commands
will mask the INT flag and disable output stage shutdown,
due to desaturation and phase errors. See the Logic
Commands and Registers section for details on masking INT
behavior and disabling the protective function.
P x_HS _G
P x_LS_G
VS _UP
Deadtime
tB _LANK
Phase x Output Voltage Shorted to VSUP
PHASE x
0.5VSUP
Correct Phase x Output Voltage
-VD
Fault
Correct
Phase Error
Figure 16. Short to Supply Detection
Phase Comparator
Faults could also be detected as Phase Errors. A phase
error is generated if the output signal (at Px_HS_S) does not
properly reflect the drive conditions.
A phase error is detected by a Phase Comparator. The
Phase Comparator compares the voltage at the Px_HS_S
node with a reference of one half the voltage at the VSUP pin.
A High Side phase error (which will also trigger the
Desaturation Detector) occurs when the High Side FET is
commanded on, and Px_HS_S is still low at the end of the
deadtime and blanking time duration. Similarly, a LS phase
error occurs when the Low Side FET is commanded on, and
the Px_HS_S is still high at the end of the deadtime and
blanking time duration.
The Phase Error Flag is the triple OR of phase errors from
each phase. Each phase error is the OR of the High Side and
Low Side phase errors. This flag can generate an interrupt if
the appropriate mask bit is set. The INT will be held in the
High state until the fault is removed, and the appropriate bit
in the Status Register 0 is cleared by the CLINT1 command.
This fault reporting mechanism is described in detail in the
Logic Commands and Registers section.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33937A
27