MC33937 Datasheet, PDF (25/48 Pages) Freescale Semiconductor, Inc – Three Phase Field Effect Transistor Pre-driver

FUNCTIONAL INTERNAL BLOCK DESCRIPTION
The Px_HS and Px_LS logic inputs are edge sensitive.
This means the leading edge on an input will cause the
complementary output to immediately turn off and the
selected one to turn on after the deadtime delay as illustrated
in Figure 13.
The deadtime delay timer always starts at the time a FET
is commanded off and prevents the complementary FET from
being commanded on until after the deadtime has elapsed.
Commands to turn on the complementary FET after the
deadtime has elapsed are executed immediately without any
further delay (see Figure 6 and Figure 13).
PA _HS
PA_LS
PA_ H S_ G
De adt ime
De lay
PA_LS_G
Figure 13. Edge Sensitive Logic Inputs (Phase A)
LOW SIDE AND BOOTSTRAP SUPPLY (VLS)
This is the portion of the IC providing current to recharge
the bootstrap capacitors. It also supplies the peak currents
required for the low side gate drivers.
The power for the gate drive circuits is provided by VLS
which is supplied from the VPWR pin. This pin can be
connected to system battery voltage and is capable of
withstanding up to the full load dump voltage of the system.
However, the IC only requires a low-voltage supply on this
pin, typically 13 to 16 V. Higher voltages on this pin will
increase the IC power dissipation.
In 12 V systems the supply voltage can fall as low as 6.0 V.
This limits the gate voltage capable of being applied to the
FETs and reduces system performance due to the higher
FET on-resistance. To allow a higher gate voltage to be
supplied, the IC also incorporates a charge pump. The
switches and control circuitry are internal; the capacitors and
diodes are external (see Figure 22).
LOW SIDE DRIVERS
These three drivers turn on and off the external Low Side
FETs. The circuits provide a low-impedance drive to the gate,
ensuring the FETs remain off in the presence of high dV/dt
transients on their drains. Additionally, these output drivers
isolate the other portions of the IC from currents capable of
being injected into the substrate due to rapid dV/dt transients
on the FET drains.
Low Side drivers switch power from VLS to the gates of the
Low Side FETs. The Low Side drivers are capable of
providing a typical peak current of 2.0 A. This gate drive
current may be limited by external resistors in order to
achieve a good trade-off between the efficiency and EMC
(Electro-Magnetic Compatibility) compliance of the
application. the Low Side driver uses high side PMOS for turn
on and low side isolated LDMOS for turn off. The circuit
ensures the impedance of the driver remains low, even
during periods of reduced current. Current limit is blanked
immediately after subsequent input state change in order to
ensure device stays off during dV/dt transients.
HIGH SIDE DRIVERS
These three drivers switch the voltage across the
bootstrap capacitor to the external high side FETs. The
circuits provide a low-impedance drive to the gate, ensuring
the FETs remain off in the presence of high dV/dt transients
on their sources. Further, these output drivers isolate the
other portions of the IC from currents capable of being
injected into the substrate due to rapid dV/dt transients on the
FETs.
The high side drivers deliver power from their bootstrap
capacitor to the gate of the external high side FET, thus
turning the high side FET on. The high side driver uses a level
shifter, which allows the gate of the external high side FET to
be turned off by switching to the high side FET source.
The gate supply voltage for the high side drivers is
obtained from the bootstrap supply, so, a short time is
required after the application of power to the IC to charge the
bootstrap capacitors. To ensure this occurrence, the internal
control logic will not allow a high side switch to be turned on
after entering the ENABLE state until the corresponding low
side switch is enabled at least once. Caution must be
exercised after a long period of inactivity of the low side
switches to verify the bootstrap capacitor is not discharged. It
will be charged by activating the low side switches for a brief
period, or by attaching external bleed resistors from the
HS_S pins to GND. See Initialization Requirements on page
37.
In order to achieve a 100% duty cycle operation of the High
Side external FETs, a fully integrated trickle charge pump
provides the charge necessary to maintain the external FET
gates at fully enhanced levels. The trickle charge pump has
limited ability to supply external leakage paths while
performing it’s primary function. The graph in Figure 11
shows the typical margin for supplying external current loads.
These limits are based on maintaining the voltage at CBOOT
at least 3.0 V greater than the voltage on the HS_S for that
phase. If this voltage differential becomes less than 3.0 V, the
corresponding high side FET will most likely not remain fully
enhanced and the high side driver may malfunction due to
insufficient bias voltage between CBOOT and HS_S.
The slew rate of the external output FET is limited by the
driver output impedance, overall (external and internal) gate
resistance and the load capacitance. To ensure the Low Side
FET is not turned on by a large positive dV/dt on the drain of
the Low Side FET, the turn-on slew rate of the High Side
should be limited. If the slew rate of the High Side is limited
Analog Integrated Circuit Device Data
Freescale Semiconductor
33937A
25