MC33937 Datasheet, PDF (4/48 Pages) Freescale Semiconductor, Inc – Three Phase Field Effect Transistor Pre-driver

PIN CONNECTIONS
Table 1. 33937A Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.
Pin
Pin Name Pin Function
Formal Name
Definition
12
PA_HS Digital Input Phase A High Side ^{Active low input logic signal enables the High Side Driver for Phase A}
13
PA_LS
Digital Input Phase A Low Side Active high input logic signal enables the Low Side Driver for Phase A
14
VDD
Analog Output VDD Regulator
VDD regulator output capacitor connection.
15
PB_HS Digital Input Phase B High Side ^{Active low input logic signal enables the High Side Driver for Phase B}
16
PB_LS
Digital Input Phase B Low Side Active high input logic signal enables the Low Side Driver for Phase B
17
INT
Digital Output
Interrupt
Interrupt pin output
18
CS
Digital Input
Chip Select
Chip Select input. It frames SPI commands and enables SPI port
19
SI
Digital Input
Serial In
Input data for SPI port. Clocked on the falling edge of SCLK, MSB first
20
SCLK
Digital Input
Serial Clock
Clock for SPI port and typically is 3.0 MHz
21
SO
Digital Output
Serial Out
Output data for SPI port. Tri-state until CS becomes low
22
PC_LS
Digital Input Phase C Low Side Active high input logic signal enables the Low Side Driver for Phase C
23
PC_HS Digital Input Phase C High Side ^{Active low input logic signal enables the High Side Driver for Phase C}
24
AMP_OUT Analog Output Amplifier Output ^{Output of the current-sensing amplifier}
25
AMP_N Analog Input
Amplifier Invert
Inverting input of the current-sensing amplifier
26
AMP_P Analog Input Amplifier Non-Invert Non-inverting input of the current-sensing amplifier
27
OC_OUT Digital Output Over-current Out ^{Totem pole digital output of the Over-current Comparator}
28
OC_TH Analog Input Over-current Threshold ^{Threshold of the over-current detector}
29
VSS
Ground Voltage Source Supply Ground reference for logic interface and power supplies
30, 31
GND
Ground
Ground
Substrate and ESD reference, connect to VSS
32
VLS_CAP Analog Output VLS Regulator Output ^{VLS Regulator connection for additional output capacitor, providing low-}
Capacitor
impedance supply source for Low Side Gate Drive
34
PC_LS_S Power Input Phase C Low Side ^{Source connection for Phase C Low Side FET}
Source
35
PC_LS_G Power Output Phase C Low Side Gate Gate drive output for Phase C Low Side
Drive
36
PC_HS_S Power Input Phase C High Side ^{Source connection for Phase C High Side FET}
Source
37
PC_HS_G Power Output Phase C High Side ^{Gate Drive for output Phase C High Side FET}
Gate Drive
38
PC_BOOT Analog Input Phase C Bootstrap Bootstrap capacitor for Phase C
39
PB_LS_S Power Input Phase B Low Side ^{Source connection for Phase B Low Side FET}
Source
40
PB_LS_G Power Output Phase B Low Side Gate Gate Drive for output Phase B Low Side
Drive
41
PB_HS_S Power Input Phase B High Side ^{Source connection for Phase B High Side FET}
Source
42
PB_HS_G Power Output Phase B High Side ^{Gate Drive for output Phase B High Side}
Gate Drive
43
PB_BOOT Analog Input Phase B Bootstrap Bootstrap capacitor for Phase B
44
PA_LS_S Power Input Phase A Low Side ^{Source connection for Phase A Low Side FET}
Source
33937A
4
Analog Integrated Circuit Device Data
Freescale Semiconductor