MC33937 Datasheet, PDF (37/48 Pages) Freescale Semiconductor, Inc – Three Phase Field Effect Transistor Pre-driver

FUNCTIONAL DEVICE OPERATION
INITIALIZATION REQUIREMENTS
INITIALIZATION REQUIREMENTS
The 33937A provides safe, dependable gate control for 3
phase BLDC motor control units when it is properly
configured. However, if improperly initialized, the high side
gate drive can be left in a high-impedance mode which will
allow charge to accumulate from external sources, eventually
turning on the high side output transistor. It is prudent to
follow a well defined initialization procedure which will
establish known states on the gates of all the phase drivers
before any current flows in the motor.
RECOVERY FROM SLEEP MODE (RESET)
The output gate drive is pulled low with the hold off circuit
as long as VLS is low, there is a Power On Reset condition or
+5V is low. These conditions are present during a Reset
condition. When first coming out of a reset condition, the gate
drive circuits are in a high-impedance state until the first
command is given for operation. After the Reset line goes
high, the supplies begin to operate and the hold off circuit is
deactivated. The phase input lines will not have any effect on
the gate drive until both ENABLE1 and ENABLE2 go high
and even then, the low side gate must be commanded on
before the high side gate can be operated. This is to insure
the bootstrap capacitor has been charged before
commencing normal operation. Then the high side gate must
be commanded on and then off to initialize the output latches.
A proper initialization sequence will place the output gate
drives in a low-impedance known condition prior to releasing
the device for normal operation.
A valid initialization sequence would go something like
this:
1. RESET goes high (ENABLE1 and ENABLE2 remain
low)
2. SPI commands to configure valid interrupts, DESAT
mode and Dead Time are issued
3. SPI command to clear all interrupt conditions
4. ENABLE1 and ENABLE2 are set HIGH (LS outputs are
now enabled)
5. PA_LS, PB_LS and PC_LS are toggled HIGH for about
1us (HS outputs are enabled, but not latched)
6. Toggle nPA_HS, nPB_HS and nPC_HS LOW for
DEAD TIME plus at least 0.1us (HS outputs are now
latched and operational).
End of initialization.
Doing step 6 simultaneously on all HS inputs will place the
motor into High Side Recirculation mode and will not cause
motion during the time they are ON.
This action will force the High Side gate drive out of tri-
state mode and leave it with the HS_G shorted to HS_S on
all phases. The HS output FETs will be OFF and ready for
normal motor control.
Step 5 and step 6 can be done on all the stated inputs
simultaneously. It may be desirable for the HS (step 6) to be
toggled simultaneously to prevent current from flowing in the
motor during initialization.
Note the inputs PA_LS, PB_LS, PC_LS, nPA_HS,
nPB_HS and nPC_HS are edge sensitive. Toggling the LS
inputs enables the HS drivers, so for the HS drivers to be
initialized correctly the edge of the input signal to the HS
drivers must come after the LS input toggle. A failure to do
this will result in the HS gate output remaining in a high-
impedance mode. This can result in an accumulation of
charge, from internal and external leakage sources, on the
gate of the HS output FET causing it to turn ON even though
the input level to the 33937A would appear to indicate it
should be OFF. When this happens, the logic of the 33937A
will allow the LS output FET to be turned ON without taking
any action on the HS gate because the logic is still indicating
that the HS gate is OFF. The initial LS input transition from
low to high needs to be after both ENABLE inputs are high
(the device in NORMAL mode) for the same reason. The
delay between ENABLE and the LS input should be 280 ns
minimum to insure the device is out of STBY mode. Once
initialized the output gate drives will continue to operate in a
low-impedance mode as commanded by the inputs until the
next reset event.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33937A
37