K50P121M100SF2 Datasheet, PDF (67/69 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

121 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
MAP
BGA
• PTC12
PTC12
UART4_RTS
_b
FB_AD27
• PTC13
PTC13
UART4_CTS
_b
FB_AD26
• PTC14
PTC14
UART4_RX
FB_AD25
• PTC15
PTC15
UART4_TX
FB_AD24
• VSS
VSS
VSS
• VDD
VDD
VDD
• PTC16
PTC16
UART3_RX
FB_CS5_b/
FB_TSIZ1/
FB_BE23_16
_BLS15_8_b
• PTC17
PTC17
UART3_TX
FB_CS4_b/
FB_TSIZ0/
FB_BE31_24
_BLS7_0_b
• PTC18
PTC18
UART3_RTS
_b
FB_TBST_b/
FB_CS2_b/
FB_BE15_8_
BLS23_16_b
• PTC19
PTC19
UART3_CTS
_b
FB_CS3_b/ FB_TA_b
FB_BE7_0_
BLS31_24_b
• PTD0
PTD0
SPI0_PCS0 UART2_RTS
_b
FB_ALE/
FB_CS1_b/
FB_TS_b
• PTD1
/ADC0_SE5b /ADC0_SE5b PTD1
SPI0_SCK UART2_CTS
_b
FB_CS0_b
• PTD2
PTD2
SPI0_SOUT UART2_RX
FB_AD4
• PTD3
PTD3
SPI0_SIN UART2_TX
FB_AD3
• PTD4
PTD4
SPI0_PCS1 UART0_RTS FTM0_CH4 FB_AD2 EWM_IN
_b
• PTD5
/ADC0_SE6b /ADC0_SE6b PTD5
SPI0_PCS2 UART0_CTS FTM0_CH5 FB_AD1
_b
EWM_OUT_
b
• PTD6
/ADC0_SE7b /ADC0_SE7b PTD6
SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0
• VSS
VSS
VSS
• PTD7
PTD7
CMT_IRO UART0_TX FTM0_CH7
FTM0_FLT1
• PTD8
DISABLED
PTD8
I2C0_SCL UART5_RX
FB_A16
• PTD9
DISABLED
PTD9
I2C0_SDA UART5_TX
FB_A17
• PTD10
DISABLED
PTD10
UART5_RTS
_b
FB_A18
• PTD11
DISABLED
PTD11
SPI2_PCS0 UART5_CTS SDHC0_CLK
_b
IN
FB_A19
• PTD12
DISABLED
PTD12
SPI2_SCK
SDHC0_D4
FB_A20
• PTD13
DISABLED
PTD13
SPI2_SOUT
SDHC0_D5
FB_A21
• PTD14
DISABLED
PTD14
SPI2_SIN
SDHC0_D6
FB_A22
Pinout
EzPort
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
67