K50P121M100SF2 Datasheet, PDF (65/69 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

121 Pin Name
MAP
BGA
• PTA1
• PTA2
• PTA3
• PTA4
• PTA12
Default
JTAG_TDI/
EZP_DI
JTAG_TDO/
TRACE_SW
O/EZP_DO
JTAG_TMS/
SWD_DIO
NMI_b/
EZP_CS_b
CMP2_IN0
ALT0
TSI0_CH2
TSI0_CH3
TSI0_CH4
TSI0_CH5
CMP2_IN0
ALT1
PTA1
PTA2
PTA3
PTA4
PTA12
• PTA13
CMP2_IN1 CMP2_IN1 PTA13
• PTA14
DISABLED
PTA14
• PTA15
• VDD
• VSS
• PTA18
DISABLED
VDD
VSS
EXTAL
VDD
VSS
EXTAL
PTA15
PTA18
• PTA19
XTAL
XTAL
PTA19
• RESET_b
• PTA24
• PTA25
• PTA26
• PTA27
• PTA28
• PTA29
• PTB0
• PTB1
• PTB2
• PTB3
• PTB6
• PTB7
• PTB8
RESET_b RESET_b
DISABLED
PTA24
DISABLED
PTA25
DISABLED
PTA26
DISABLED
PTA27
DISABLED
PTA28
DISABLED
PTA29
/ADC0_SE8/ /ADC0_SE8/ PTB0
ADC1_SE8/ ADC1_SE8/
TSI0_CH0 TSI0_CH0
/ADC0_SE9/ /ADC0_SE9/ PTB1
ADC1_SE9/ ADC1_SE9/
TSI0_CH6 TSI0_CH6
/
/
PTB2
ADC0_SE12/ ADC0_SE12/
TSI0_CH7 TSI0_CH7
/
/
PTB3
ADC0_SE13/ ADC0_SE13/
TSI0_CH8 TSI0_CH8
/ADC1_SE12 /ADC1_SE12 PTB6
/ADC1_SE13 /ADC1_SE13 PTB7
PTB8
ALT2
ALT3
ALT4
ALT5
UART0_RX FTM0_CH6
UART0_TX FTM0_CH7
UART0_RTS FTM0_CH0
_b
FTM0_CH1
FTM1_CH0
FTM1_CH1
SPI0_PCS0 UART0_TX
SPI0_SCK UART0_RX
FTM0_FLT2
FTM1_FLT0
FTM_CLKIN
0
FTM_CLKIN
1
I2C0_SCL FTM1_CH0
I2C0_SDA FTM1_CH1
I2C0_SCL UART0_RTS
_b
I2C0_SDA UART0_CTS
_b
UART3_RTS
_b
FB_AD23
FB_AD22
FB_AD21
Pinout
ALT6
ALT7
EzPort
JTAG_TDI EZP_DI
JTAG_TDO/ EZP_DO
TRACE_SW
O
JTAG_TMS/
SWD_DIO
NMI_b
EZP_CS_b
I2S0_TXD FTM1_QD_P
HA
I2S0_TX_FS FTM1_QD_P
HB
I2S0_TX_BC
LK
I2S0_RXD
LPT0_ALT1
FB_A29
FB_A28
FB_A27
FB_A26
FB_A25
FB_A24
FTM1_QD_P
HA
FTM1_QD_P
HB
FTM0_FLT3
FTM0_FLT0
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
65