K50P121M100SF2 Datasheet, PDF (32/69 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Peripheral operating requirements and behaviors
Table 21. NVM reliability specifications (continued)
Symbol Description
t_nvmretp100 Data retention after up to 100 cycles
n_nvmcycp Cycling endurance
Min.
15
10 K
Typ.¹
TBD
TBD
Max.
—
—
Unit
years
cycles
Notes
2
3
1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to
25°C. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin
EB618.
2. Data retention is based on T_javg = 55°C (temperature profile over the lifetime of the application).
3. Cycling endurance represents number of program/erase cycles at -40°C ≤ T_j ≤ 125°C.
6.4.2 EzPort Switching Specifications
Table 22. EzPort switching specifications
Num
EP1
EP1a
Description
Operating voltage
EZP_CK frequency of operation (all commands except
READ)
EZP_CK frequency of operation (READ command)
Min.
2.7
—
—
EP2
EZP_CS negation to next EZP_CS assertion
EP3
EZP_CS input valid to EZP_CK high (setup)
EP4
EZP_CK high to EZP_CS input invalid (hold)
EP5
EZP_D input valid to EZP_CK high (setup)
EP6
EZP_CK high to EZP_D input invalid (hold)
EP7
EZP_CK low to EZP_Q output valid (setup)
EP8
EZP_CK low to EZP_Q output invalid (hold)
EP9
EZP_CS negation to EZP_Q tri-state
2 x t_{EZP_CK}
5
5
2
5
—
0
—
Max.
3.6
f_SYS/2
f_SYS/8
—
—
—
—
—
12
—
12
Unit
V
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
32
Preliminary
Freescale Semiconductor, Inc.