K50P121M100SF2 Datasheet, PDF (14/69 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

General
5.1.4 Power mode transition operating behaviors
All specifications except t_POR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 100 MHz
• Bus and FlexBus clocks = 50 MHz
• Flash clock = 25 MHz
Symbol
t_POR
Table 5. Power mode transition operating behaviors
Description
Min.
Max.
Unit
After a POR event, amount of time from the point V_DD
—
300
μs
reaches 1.8V to execution of the first instruction
across the operating temperature range of the chip.
RUN → VLLS1 → RUN
• RUN → VLLS1
—
4.1
μs
• VLLS1 → RUN
—
123.8
μs
Notes
1
RUN → VLLS2 → RUN
• RUN → VLLS2
• VLLS2 → RUN
—
4.1
μs
—
49.3
μs
RUN → VLLS3 → RUN
• RUN → VLLS3
• VLLS3 → RUN
—
4.1
μs
—
49.2
μs
RUN → LLS → RUN
• RUN → LLS
• LLS → RUN
—
4.1
μs
—
5.9
μs
RUN → STOP → RUN
• RUN → STOP
• STOP → RUN
—
4.1
μs
—
4.2
μs
RUN → VLPS → RUN
• RUN → VLPS
• VLPS → RUN
—
4.1
μs
—
5.8
μs
1. Normal boot (FTFL_OPT[LPBOOT]=1)
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
14
Preliminary
Freescale Semiconductor, Inc.