FXLC95000CL Datasheet, PDF (6/38 Pages) Freescale Semiconductor, Inc – Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform

General Description
INT_I
BKGD/MS
Interrupt
controller
16 KB
RAM
ColdFire
V1
CPU
16 KB
ROM
128 KB
Flash
memory
SSB
SCLK
MOSI
MISO
SDA0
SCL0
3-axis
accelerometer
transducer
Temperature
sensor
Drive circuit
C2V
Analog Front End
ADC
Peripheral
16
bus interface
Trim
SPI slave
I²C slave
RESETB
System Integration
Module
Control and
8
mailbox
register set
8
SP_SCR[PS]
External
clock
domain
Internal
clock
domain
16
Flash
controller
8
I²C master
/ ^SDA1,SCL1
16
SPI master
/
MOSI, MISO,
SCLK2. SSB2
8
2 x 8 Port
control
8
16-bit modulo
timer
16
Programmable
Delay Block
/
PDB_A,
PDB_B
8
Two-channel
TPM
/
TPMCH0,
TPMCH1
8
Clock module
(16 MHz)
16
RGPIO[15:0]
/
RGPIO0, ... ,
RGPIO15
Figure 1. Block diagram of the FXLC95000CL
A block level view of the FXLC95000CL platform is shown in Figure 1 and can be
summarized at a high level as an analog/mixed mode subsystem associated with a
digital engine.
The analog sub-system is composed of:
• A 3-axis MEMS transducer
• An Analog Front End (AFE) with:
• A capacitance-to-voltage converter
• An analog-to-digital converter
• A temperature sensor
The digital sub-system is composed of:
• A 32-bit, ColdFire V1 CPU with Background Debug Module (BDM)
• Memory: RAM, ROM, and flash
• Rapid General Purpose Input/Output (RGPIO) port control logic
• Timer functions:
• Modulo Timer Module (MTIM16)
• Programmable Delay Timer (PDB)
• General-Purpose Timer/Pulse-Width Modulation Module (TPM)
6
Freescale Semiconductor, Inc.
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.