FXLC95000CL Datasheet, PDF (12/38 Pages) Freescale Semiconductor, Inc – Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform

General Description
MS = 1'b1, at exit from reset → boot to run mode.
State after reset: BKGD. The BKGD pin is a bidirectional, pseudo-open-drain pin used
for communications with a debug environment.
Programmable Delay Block: PDB_A, PDB_B
These are the two outputs of the programmable delay block (PDB). Normally, the PDB
is used to schedule internal events at some fixed interval(s) relative to start of either the
analog or digital phase. By bringing the PDB outputs to these pins, it becomes possible
for the FXLC95000CL to initiate some external event, also relative to start of analog or
digital phase. For more information, refer to the FXLC95000CL Hardware Reference
Manual.
Timer: TPMCH0 and TPMCH1
These pins are the outputs for a general modulo 16 timer and general input/output
capture (TPM) and pulse width modulation (PWM) functions.
Slave SPI Interface: SCLK, MOSI, MISO, SSB
Slave SPI clock, master-output slave-input, master-input slave-output, and slave-select
signals. The FXLC95000CL may be controlled via this serial port or via the slave I²C
interface.
State at reset: In reset, these pins are configured according to I²C and RGPIO[3:2]
functions listed above. The pin may be reconfigured for SPI use as part of the boot
process.
Master SPI Interface: SCLK1, MOSI1, MISO1, SSB1
Master SPI clock, master-output slave-input, master-input slave-output, and slave-select
signals.
State at reset: In reset, these pins are configured as RGPIO[13:10] functions listed
above.
4.3 System connections
The FXLC95000CL platform offers the choice of connecting to a host processor
through either an I²C or SPI interface. It can also act as a master controller for I²C or
SPI peripherals and analog sensors.
12
Freescale Semiconductor, Inc.
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.