FXLC95000CL Datasheet, PDF (11/38 Pages) Freescale Semiconductor, Inc – Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform

General Description
• RGPIO[13:10, 8:2]: Pin mux registers for these bits are configured as RGPIO.
Pullups are disabled. RGPIO functionality can be enabled via
RGPIO_ENB[13:10, 8:2].
• RGPIO[9]: Inactive. BKGD/MS owns the pin at reset
• RGPIO[1:0]: inactive. SDA0 and SCL0 own the pin at reset.
Configuration details:
• RGPIO[15:14] are configured as Master I²C port at reset when
RGPIO_ENB[15:14]=00 and PMCR[A3]=PMCR[A2]=00 or 10. They can only
be configured as RGPIO when PMCR[A3]=PMCR[A2]=01. RGPIO_ENB[15:14]
must also be set to 11 for them to assume RGPIO functionality.
• RGPIO_ENB[13:10] are used to configure RGPIO[13:10].
• Pin function selections are made via the SIM pin mux registers for RGPIO[9:0].
Interrupts: INT_I
This input pin may be used to wake the CPU from a deep-sleep mode. It can be
programmed to trigger on either rising or falling edge or high or low level. This pin
operates as a level 7 (high priority) interrupt.
Interrupts: INT_O
RGPIO5 (pin 11) can be configured to function as an interrupt output pin. This
interrupt can be asserted via software when a command response packet has been
stored on the slave port mailboxes and is ready for the host to read. The host will see
the interrupt and can read the data from the FXLC95000CL platform. The
FXLC95000CL will automatically clear the interrupt once it recognizes that the
response packet is being transmitted. This clearing action occurs while the packet is
being read and prevents the host from falsely recognizing the same interrupt after the
packet read is complete.
State at reset: Pin muxing is set to RGPIO5 mode.
Debug/Mode Control: BKGD/MS
At power-up, this pin operates as Mode Select. If low during power-up, the CPU will
boot into debug halt mode. If high, the CPU will boot normally and run code. After
power-on reset, this pin operates as a bidirectional, single-wire Background Debug
port. CodeWarrior uses the Background Debug port to download code into on-chip
RAM and flash, and for debugging that code using breakpoints and single stepping.
State at reset: Mode Select (MS).
MS = 1'b0, at exit from reset → boot to debug halt mode.
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
11
Freescale Semiconductor, Inc.