FXLC95000CL Datasheet, PDF (30/38 Pages) Freescale Semiconductor, Inc – Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform

Mechanical and Electrical Specifications
3. Set-up time in slave-transmitter mode is 1 system-clock period (16 MHz = 62.5 ns). There is no FIFO on the I²C.
4. A fast-mode, I²C bus device can be used in a standard mode I²C bus system, but the requirement t_{SU; DAT} ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
According to the standard mode, I²C bus specification, if such a device stretches the LOW period of the SCL signal, it
must output the next data bit to the SDA line trmax + t_SU; DAT = 1000 + 250 = 1250 ns before the SCL line is released.
5.11.3 SPI interfaces (slave and master)
Figure 11 and Table 14 describe the timing requirements for the SPI system.
SS
(input)
1
12
11 3
SCLK
(input)
MISO
(output)
MOSI
(input)
2
4
4
7
SLAVE MSB OUT
5
6
MSB IN
9
BIT 6...1
BIT 6...1
8
10
10
SLAVE LSB OUT
Not defined
(see note)
LSB IN
Note:
Not defined—normally the MSB of the character just received.
Figure 11. Slave and master SPI timing
Drawing
Number
—
1
2
3
4
Function
Table 14. Slave and master SPI timing
Symbol
Min
Operating frequency
SCLK period
Enable lead time
Enable lag time
Clock (SCLK) high or low time
f_op
0
t_SCLK
4
t_Lead
0.5
t_Lag
0.5
t_WSCLK
200
Table continues on the next page...
Max
F_OPH/4
—
—
—
—
Unit
Hz
t_CYCH
t_CYCH
t_CYCH
ns
30
Freescale Semiconductor, Inc.
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.