FXLC95000CL Datasheet, PDF (29/38 Pages) Freescale Semiconductor, Inc – Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform

Mechanical and Electrical Specifications
5.11.1 Slave I²C
Table 12. I²C speed ranges
Mode
Standard
Fast
Fast +
High-speed
supported
Max Baud Minimum
Rate
Bit Time
(f_SCL)
100 KHz
10 μs
400 KHz 2.5 μs
1 MHz
1 μs
2.0 MHz 0.5 μs
Minimum SCL
Low
(t_LOW)
4.7 μs
1.3 μs
500 ns
200 ns
Minimum SCL
High
(t_HIGH)
4 μs
0.6 μs
260 ns
200 ns
Min Data Set-
up Time
(t_{SU; DAT})
250 ns
100 ns
50 ns
10 ns
Min/Max Data Hold
Time
(t_{HD; DAT})
0 μs/3.45 μs¹
0 μs/0.9 μs¹
0 μs/0.45 μs¹
0 ns/70 ns (100 pf)²
1. The maximum t_HD;DAT must be at least a transmission time less than t_VD;DAT or t_VD;ACK. For details, see the I²C
standard.
2. Timing met with IFE = 0, DS = 1, and SE = 1. For more information, refer to Port Control Registers in the
FXLC95000CL Hardware Reference Manual.
5.11.2 Master I²C Timing
The master I²C should only be used when the system clock is running at full speed.
Do not attempt to use the master I²C across frames in which a portion of the time is
spent in low-speed mode.
Table 13. Master I²C timing
Characteristic
Symbol
SCL clock frequency
Hold time (repeated) START condition. After
this period, the first clock pulse is generated.
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data Hold Time for I²C bus devices
Data set-up time
Set-up time for STOP condition
Bus free time between STOP and START
condition
Pulse width of spikes that must be suppressed
by the input filter
f_SCL
t_{HD; STA}
t_LOW
t_HIGH
t_{SU; STA}
t_{HD; DAT}
t_{SU; DAT}
t_{SU; STO}
t_BUF
t_SP
Standard Mode
Min
Max
0
100
4.0
—
4.7
—
4.0
—
4.7
—
0¹
3.45²
250
—
4.0
—
4.7
—
N/A
N/A
Fast Mode
Min
Max
0
400
0.6
—
1.3
—
0.6
—
0.6
—
0¹
0.9²
100^{3, 4}
—
0.6
—
1.3
—
0
50
Unit
kHz
μs
μs
μs
μs
μs
ns
μs
μs
μs
1. The master mode I²C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum t_{HD; DAT} must be met only if the device does not stretch the LOW period (t_LOW) of the SCL signal.
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
29
Freescale Semiconductor, Inc.