K20P144M100SF2 Datasheet, PDF (59/67 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Pinout
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to www.freescale.com and perform a keyword search for
the drawing’s document number:
If you want the drawing for this package
Then use this document number
144-pin LQFP
98ASS23177W
144-pin MAPBGA
98ASA00222D
y _{8 Pinout}
ar _{8.1 K20 Signal Multiplexing and Pin Assignments}
The following table shows the signals available on each pin and the locations of these
in ^{pins on the devices supported by this document. The Port Control Module is responsible}
for selecting which ALT functionality is available on each pin.
144 144 Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
QFP BGA
lim ^{— C10 NC}
— B10 NC
— A10 NC
— L5 NC
e _{— M5 NC}
r _{1 D3 ADC1_SE4a ADC1_SE4a PTE0}
SPI1_PCS1 UART1_TX SDHC0_D1
2 D2 ADC1_SE5a ADC1_SE5a PTE1
SPI1_SOUT UART1_RX SDHC0_D0
P ^{3 D1 ADC1_SE6a ADC1_SE6a PTE2}
SPI1_SCK UART1_CTS SDHC0_DCL
ALT6
I2C1_SDA
I2C1_SCL
ALT7
EzPort
_b
K
4 E4 ADC1_SE7a ADC1_SE7a PTE3
SPI1_SIN
UART1_RTS SDHC0_CMD
_b
5 E5 VDD
VDD
6 F6 VSS
VSS
7 E3 DISABLED
PTE4
SPI1_PCS0 UART3_TX SDHC0_D3
8 E2 DISABLED
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2
9 E1 DISABLED
PTE6
SPI1_PCS3 UART3_CTS I2S0_MCLK
_b
I2S0_CLKIN
10 F4 DISABLED
PTE7
UART3_RTS I2S0_RXD
_b
11 F3 DISABLED
PTE8
UART5_TX I2S0_RX_FS
12 F2 DISABLED
PTE9
UART5_RX I2S0_RX_BC
LK
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
59