K20P144M100SF2 Datasheet, PDF (34/67 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 21. EzPort switching specifications (continued)
Num
Description
Min.
Max.
Unit
EP1
EZP_CK frequency of operation (all commands except
READ)
—
f_SYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
—
f_SYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x t_{EZP_CK}
—
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
—
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
—
ns
EP5
EZP_D input valid to EZP_CK high (setup)
EP6
EZP_CK high to EZP_D input invalid (hold)
EP7
EZP_CK low to EZP_Q output valid (setup)
EP8
EZP_CK low to EZP_Q output invalid (hold)
EP9
EZP_CS negation to EZP_Q tri-state
EZP_CK
2
—
5
—
—
12
y ₀
—
inar^—
12
ns
ns
ns
ns
ns
EZP_CS
EZP_Q (output)
EZP_D (input)
EP3
EP4
EP2
EP9
lim ^EP7
EP8
Pre^EP5
EP6
Figure 10. EzPort Timing Diagram
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
34
Preliminary
Freescale Semiconductor, Inc.