K20P144M100SF2 Datasheet, PDF (57/67 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
I2S_BCLK (input)
S11
S12
S12
I2S_FS (output)
S15
S13
S16
S14
I2S_FS (input)
S15
S15
S16
S16
I2S_TXD
S17
S18
y ^I2S_RXD
Figure 24. I²S timing — slave modes
ar _{6.9 Human-machine interfaces (HMI)}
in _{6.9.1 General Switching Specifications}
These general purpose specifications apply to all signals configured for GPIO, SCI,
lim ^{FlexCAN, CMT, I2C, and IEEE 1588 timer signals.}
Table 43. General switching specifications
Pre ^Symbol
Description
GPIO pin interrupt pulse width (digital glitch filter disa‐
bled) — Synchronous path
GPIO pin interrupt pulse width (digital glitch filter disa‐
bled, analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter disa‐
Min.
1.5
100
16
Max.
—
—
—
Unit
Bus clock
cycles
ns
ns
Notes
1
2
2
bled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
TBD
—
Mode select (EZP_CS) hold time after reset deasser‐
2
tion
—
Bus clock
cycles
Port rise and fall time (high drive strength)
3
• Slew disabled
—
12
ns
• Slew enabled
—
36
ns
Port rise and fall time (low drive strength)
• Slew disabled
• Slew enabled
4
—
32
ns
—
36
ns
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
57