K20P144M100SF2 Datasheet, PDF (53/67 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
6.8.5 DSPI Switching Specifications (High-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 38. Master Mode DSPI Timing (High-speed mode)
Num
Description
Min.
Max.
Unit
Operating voltage
Frequency of operation
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
DS3
DSPI_PCSn to DSPI_SCK output valid
DS4
DSPI_SCK to DSPI_PCSn output hold
DS5
DSPI_SCK to DSPI_SOUT valid
DS6
DSPI_SCK to DSPI_SOUT invalid
2.7
—
y ^{2 x tBCLK}
(t_SCK/2) − 2
r _{(tSCK/2) − 2}
a(t_SCK/2) − 2
—
in^−2
3.6
25
—
(t_SCK/2) + 2
—
—
8.5
—
V
MHz
ns
ns
ns
ns
ns
ns
DS7
DSPI_SIN to DSPI_SCK input setup
DS8
DSPI_SCK to DSPI_SIN input hold
lim ^DSPI_PCSn
DSPI_SCK
e _(CPOL=0)
Pr ^DSPI_SIN
DS3
DS7
DS8
First data
DS2
Data
DS5
DS1
Last data
DS6
TBD
0
DS4
—
—
ns
ns
DSPI_SOUT
First data
Data
Last data
Num
DS9
DS10
DS11
Figure 20. DSPI Classic SPI Timing — Master Mode
Table 39. Slave Mode DSPI Timing (High-speed mode)
Operating voltage
Description
Frequency of operation
DSPI_SCK input cycle time
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
Min.
2.7
4 x t_BCLK
(t_SCK/2) − 2
—
Max.
3.6
12.5
—
(t_SCK/2 + 2
TBD
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
Unit
V
MHz
ns
ns
ns
53