K20P144M100SF2 Datasheet, PDF (56/67 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 41. _I²_{S master mode timing (continued)}
Num
Description
Min.
Max.
Unit
S5
I2S_BCLK to I2S_FS output valid
—
15
ns
S6
I2S_BCLK to I2S_FS output invalid
-2.5
—
ns
S7
I2S_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_BCLK to I2S_TXD invalid
-3
—
ns
S9
I2S_RXD/I2S_FS input setup before I2S_BCLK
20
—
ns
S10
I2S_RXD/I2S_FS input hold after I2S_BCLK
0
—
ns
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
S1
S2
S2
S3
S4
S4
S5
S9
S7
ry_S6
ina ^S10
I2S_TXD
I2S_RXD
Num
S7
S8
S9
S10
lim _{Figure 23. I2S timing — master mode}
e_{Table 42. I}2_{S alave mode timing}
r _Description
P ^{Operating voltage}
Min.
2.7
S8
Max.
Unit
3.6
V
S11
I2S_BCLK cycle time (input)
8 x t_SYS
—
ns
S12
I2S_BCLK pulse width high/low (input)
45%
55%
MCLK period
S13
I2S_FS input setup before I2S_BCLK
10
—
ns
S14
I2S_FS input hold after I2S_BCLK
3
—
ns
S15
I2S_BCLK to I2S_TXD/I2S_FS output valid
—
20
ns
S16
I2S_BCLK to I2S_TXD/I2S_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_BCLK
10
—
ns
S18
I2S_RXD hold after I2S_BCLK
2
—
ns
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
56
Preliminary
Freescale Semiconductor, Inc.