MC9S12DT128CPVE Datasheet, PDF(54/128 Page) Freescale Semiconductor, Inc

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MC9S12DT128CPVE Datasheet, PDF (54/128 Pages) Freescale Semiconductor, Inc – Device User Guide

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MC9S12DT128B Device User GFurideeeâsVc0a1.l0e9 Semiconductor, Inc.

2.2 Signal Properties Summary

Table 2-1 summarizes the pin functionality. Signals shown in bold are not available in the 80 pin

package.

Table 2-1 Signal Properties

Pin Name Pin Name Pin Name Pin Name Pin Name Powered

Function 1 Function 2 Function 3 Function 4 Function 5 by

Internal Pull

Resistor

CTRL

Reset

State

Description

EXTAL

VDDPLL NA

Oscillator Pins

XTAL

VDDPLL NA

RESET

VDDR None None External Reset

TEST

N.A.

None None Test Input

VREGEN

VDDX

Voltage Regulator

Enable Input

XFC

VDDPLL NA

NA PLL Loop Filter

BKGD

TAGHI

MODC

VDDR

Always

Background Debug,

Tag High, Mode Input

PAD[15]

AN1[7]

ETRIG1

Port AD Input,

VDDA

None

Analog Inputs,

External Trigger

Input (ATD1)

Port AD Input,

PAD[14:8] AN1[6:0]

VDDA None None Analog Inputs

(ATD1)

PAD[7]

AN0[7]

ETRIG0

Port AD Input, Analog

VDDA None None Inputs, External

Trigger Input (ATD0)

PAD[6:0] AN0[6:0]

VDDA

None

Port AD Input, Analog

Inputs (ATD0)

PA[7:0]

ADDR[15:8]/

DATA[15:8]

VDDR

PUCR/

PUPAE

Port A I/O,

Disabled Multiplexed

Address/Data

PB[7:0]

ADDR[7:0]/

DATA[7:0]

VDDR

PUCR/

PUPBE

Disabled

Port B I/O,

Multiplexed

Address/Data

PE7

NOACC

XCLKS

VDDR

PUCR/

PUPEE

Port E I/O, Access,

Clock Select

PE6

IPIPE1

MODB

PE5

IPIPE0

MODA

VDDR

Port E I/O, Pipe

While RESET pin Status, Mode Input

low:

VDDR

Down

Port E I/O, Pipe

Status, Mode Input

PE4

ECLK

VDDR

PUCR/

PUPEE

Port E I/O, Bus Clock

Output

PE3

LSTRB

TAGLO

VDDR

PUCR/

PUPEE

Port E I/O, Byte

Strobe, Tag Low

PE2

R/W

VDDR

PUCR/

PUPEE

Port E I/O, R/W in

expanded modes

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