MC9S12DT128CPVE Datasheet, PDF (116/128 Pages) Freescale Semiconductor, Inc – Device User Guide

MC9S12DT128B Device User G^Fu^rid^ee^e—^sV^c0^a1.^l0^e9 ^{Semiconductor, Inc.}
SS¹
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
1
2
4
4
5
6
MSB IN²
9
MOSI
(OUTPUT)
PORT DATA
MASTER MSB OUT²
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
12
11
BIT 6 . . . 1
10
BIT 6 . . . 1
11
3
12
LSB IN
MASTER LSB OUT
PORT DATA
Figure A-6 SPI Master Timing (CPHA =1)
Table A-18 SPI Master Mode Timing Characteristics¹
Conditions are shown in Table A-4 unless otherwise noted, C_LOAD = 200pF on all outputs
Num C
Rating
Symbol Min
Typ
Max Unit
1 P Operating Frequency
f_op
DC
1/4
f_bus
1 P SCK Period t_sck = 1./f_op
t_sck
4
2048
t_bus
2 D Enable Lead Time
t_lead
1/2
—
t_sck
3 D Enable Lag Time
t_lag
1/2
t_sck
4 D Clock (SCK) High or Low Time
t_wsck
t_bus − 30
1024 t_bus
ns
5 D Data Setup Time (Inputs)
t_su
25
ns
6 D Data Hold Time (Inputs)
t_hi
0
ns
9 D Data Valid (after SCK Edge)
t_v
25
ns
10 D Data Hold Time (Outputs)
t_ho
0
ns
11 D Rise Time Inputs and Outputs
t_r
25
ns
12 D Fall Time Inputs and Outputs
t_f
25
ns
NOTES:
1. The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent between the
Master and the Slave timing shown in Table A-19.
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