MC9S12D64 Datasheet, PDF (54/128 Pages) Freescale Semiconductor, Inc – Device User Guide V01.20

MC9S12DJ64 Device User Guide — V01.20
Table 2-1 Signal Properties
Pin Name
Function1
EXTAL
XTAL
RESET
TEST
VREGEN
XFC
BKGD
PAD15
PAD[14:08]
PAD07
PAD[06:00]
PA[7:0]
PB[7:0]
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
Pin Name
Function2
—
—
—
—
—
—
TAGHI
AN15
AN[14:08]
AN07
AN[06:00]
ADDR[15:8]/
DATA[15:8]
ADDR[7:0]/
DATA[7:0]
NOACC
IPIPE1
IPIPE0
ECLK
LSTRB
R/W
IRQ
XIRQ
KWH7
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
Pin Name Pin Name Powered
Function3 Function4 by
Internal Pull
Resistor
CTRL
Reset
State
Description
—
—
VDDPLL
—
—
Oscillator Pins
—
—
VDDR
External Reset
None None
—
—
N.A.
Test Input
—
—
VDDX
Voltage Regulator Enable Input
—
—
VDDPLL
PLL Loop Filter
MODC
—
VDDR
Always
Up
Up
Background Debug, Tag High, Mode
Input
ETRIG1
—
Port AD Input, Analog Input AN7 of
ATD1, External Trigger Input of
ATD1
—
—
VDDA
None
Port AD Inputs, Analog Inputs
None ^{AN[6:0] of ATD1}
ETRIG0
—
Port AD Input, Analog Input AN7 of
ATD0, External Trigger Input of ATD0
—
—
Port AD Inputs, Analog Inputs AN[6:0]
of ATD0
—
—
—
—
PUCR/
PUPAE
PUCR/
PUPBE
Port A I/O, Multiplexed Address/Data
Disabled
Port B I/O, Multiplexed Address/Data
XCLKS
—
PUCR/
PUPEE
Mode
depen-
dant¹
Port E I/O, Access, Clock Select
MODB
—
MODA
—
While RESET pin is Port E I/O, Pipe Status, Mode Input
low:
Down
Port E I/O, Pipe Status, Mode Input
—
—
Mode ^{Port E I/O, Bus Clock Output}
TAGLO
—
depen- _{Port E I/O, Byte Strobe, Tag Low}
—
—
VDDR
PUCR/
PUPEE
dant¹ _{Port E I/O, R/W in expanded modes}
—
—
Port E Input, Maskable Interrupt
Up
—
—
Port E Input, Non Maskable Interrupt
—
—
Port H I/O, Interrupt
—
—
Port H I/O, Interrupt
—
—
Port H I/O, Interrupt
—
—
—
—
PERH/
PPSH
Port H I/O, Interrupt
Disabled
Port H I/O, Interrupt
—
—
Port H I/O, Interrupt
—
—
Port H I/O, Interrupt
—
—
Port H I/O, Interrupt
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