MC9S12D64 Datasheet, PDF (109/128 Pages) Freescale Semiconductor, Inc – Device User Guide V01.20

MC9S12DJ64 Device User Guide — V01.20
NOTES:
1. Depending on the crystal a damping series resistor might be necessary
2. f_osc = 4MHz, C = 22pF.
3. Maximum value is for extreme cases using high Q, low frequency crystals
4. Only valid if Pierce oscillator/external clock mode is selected
A.5.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.5.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
C_p
VDDPLL
C_s
R
Phase
XFC Pin
VCO
f_osc
1
f_ref
refdv+1
∆
K_Φ
K_V
f_vco
Detector
f_cmp
Loop Divider
1
1
synr+1
2
Figure A-2 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K₁, f₁ and i_ch from Table A-16.
The grey boxes show the calculation for f_VCO = 50MHz and f_ref = 1MHz. E.g., these frequencies are used
for f_OSC = 4MHz and a 25MHz bus clock.
The VCO Gain at the desired VCO frequency is approximated by:
K_V = K₁ ⋅ e^{-(--fK--1--1--–--⋅--f-1-v--c-V--o}₌^--)- _{–100 ⋅ e}^{(---6---–0---1--–--0---50---0--}₌^--) _-90.48MHz/V
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