MC9S12D64 Datasheet, PDF (110/128 Pages) Freescale Semiconductor, Inc – Device User Guide V01.20

MC9S12DJ64 Device User Guide — V01.20
The phase detector relationship is given by:
K_Φ = – i_ch ⋅ K_V
= 316.7Hz/Ω
i_ch is the current in tracking mode.
The loop bandwidth f_C should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
f_C < ----------2-----^â‹---^ζ----^â‹---f--^r--^e----^f---------
π ⋅ _{ζ} + 1 + ζ²_
1--1--0-- ^{→ fC <} 4----f-⋅^{r--e-1---f-0- ;(ζ = 0.9)}
f_C < 25kHz
And finally the frequency relationship is defined as
n = -f-^V-f--_r-^C-_e---^Of--- = 2 ⋅ (synr + 1) = 50
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f_C=10kHz:
R = ^2-----â‹---^π---K--^â‹--_Φ-n-----^â‹---f--^C-- ^{= 2*π*50*10kHz/(316.7Hz/Ω)=9.9kΩ=~10kΩ}
The capacitance C_s can now be calculated as:
C_s = -_π----2_â‹---f--^â‹_C---^ζ--_â‹-²--R--- ≈ ^0-f--_C-.--5--_â‹-1--R-6--;(ζ = 0.9) ^{= 5.19nF =~ 4.7nF}
The capacitance C_p should be chosen in the range of:
C_s ⁄ 20 ≤ C_p ≤ C_s ⁄ 10
C_p = 470pF
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock f_cmp, the
deviation from the reference clock f_ref is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.
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