MC9S12D64 Datasheet, PDF (13/128 Pages) Freescale Semiconductor, Inc – Device User Guide V01.20

List of Tables
MC9S12DJ64 Device User Guide — V01.20
Table 0-1 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 0-2 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 1-1 Device Memory Map for MC9S12DJ64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 1-2 Device Memory Map for MC9S12D32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
$0000 - $000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) ................30
$0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control) ...............................30
$0015 - $0016 INT map 1 of 2 (HCS12 Interrupt) ............................................................31
$0017 - $0019 Reserved ..................................................................................................31
$001A - $001B Device ID Register (Table 1-4) ................................................................31
$001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, Table 1-5) ..............31
$001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) ................31
$001F - $001F INT map 2 of 2 (HCS12 Interrupt) ............................................................32
$0020 - $0027 Reserved ..................................................................................................32
$0028 - $002F BKP (HCS12 Breakpoint) .........................................................................32
$0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control) ...............................32
$0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) ................32
$0034 - $003F CRG (Clock and Reset Generator) ..........................................................33
$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels) .................................33
$0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel) ..............................36
$00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel) .......................................37
$00C8 - $00CF SCI0 (Asynchronous Serial Interface) ......................................................39
$00D0 - $00D7 SCI1 (Asynchronous Serial Interface) ......................................................39
$00D8 - $00DF SPI0 (Serial Peripheral Interface) ............................................................40
$00E0 - $00E7 IIC (Inter IC Bus) ......................................................................................40
$00E8 - $00EF BDLC (Bytelevel Data Link Controller J1850) ..........................................41
$00F0 - $00FF Reserved ..................................................................................................41
$0100 - $010F Flash Control Register (fts64k) ................................................................41
$0110 - $011B EEPROM Control Register (eets1k) ........................................................42
$011C - $011F Reserved for RAM Control Register ........................................................42
$0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) ..............................43
$0140 - $017F CAN0 (Freescale Scalable CAN - FSCAN) ..............................................44
Table 1-3 Detailed FSCAN Foreground Receive and Transmit Buffer Layout . . . . . . . . . . .45
$0180 - $023F Reserved ..................................................................................................46
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