MC9S12D64 Datasheet, PDF (3/128 Pages) Freescale Semiconductor, Inc – Device User Guide V01.20

MC9S12DJ64 Device User Guide — V01.20
Version Revision Effective
Number Date
Date
V01.06
20 Aug. 20 Aug.
2002
2002
V01.07
20 Sept. 20 Sept.
2002
2002
V01.08
25 Sept. 25 Sept.
2002
2002
V01.09
10 Oct.
2002
10 Oct.
2002
V01.10
8 Nov.
2002
8 Nov.
2002
V01.11
24 Jan.
2003
24 Jan.
2003
V01.12
31 Mar.
2003
31 Mar.
2003
V01.13
20 May
2003
20 May
2003
V01.14
10 June 10 June
2003
2003
Author
Description of Changes
NVM electricals updated
Subsection "Detailed Register Map: Address corrections
Preface, Table "Document references": added OSC User Guide
New section "Oscillator (OSC) Block Description"
Electrical Characteristics:
-> Section "General": removed preliminary disclaimer
->Table "Supply Current Characteristics":
changed max Run IDD from 65mA to 50mA
changes max Wait IDD from 40mA to 30mA
changed max Stop IDD from 50uA to 100uA
Section HCS12 Core Block Description: mentioned alternate clock
of BDM to be equivalent to oscillator clock
Table "5V I/O Characteristics": Corrected Input Leakage Current to
+/- 1 uA
Section "Part ID assignment": Located on start of next page for
better readability
Added MC9S12A64 derivative to cover sheet and "Derivative
Differences" Table
Corrected in footnote of Table "PLL Characteristics": f_OSC = 4MHz
Renamed "Preface" section to "Derivative Differences and
Document references". Added details for derivatives missing CAN0
and/or BDLC
Table "ESD and Latch-up Test Conditions": changed pulse numbers
from 3 to 1
Table "ESD and Latch-Up Protection Characteristics": changed
parameter classification from C to T
Table "5V I/O Characteristics": removed foot note from "Input
Leakage Current"
Table " Supply Current Characteristics": updated Stop and Pseudo
Stop currents
Subsection "Detailed Register Map": Corrected several entries
Subsection "Unsecuring the Microcontroller": Added more details
Table "Operating Conditions": improved footnote 1 wording, applied
footnote 1 to PLL Supply Voltage.
Tables "SPI Master/Slave Mode Timing Characteristics: Corrected
Operating Frequency
Appendix ’NVM, Flash and EEPROM’: Replaced ’burst
programming’ by ’row programming
Table "Operating Conditions": corrected minimum bus frequency to
0.25MHz
Section "Feature List": ECT features changed to "Four pulse
accumulators ..."
Replaced references to HCS12 Core Guide by the individual
HCS12 Block guides
Table "Signal Properties" corrected pull resistor reset state for PE7
and PE4-PE2.
Table "Absolute Maximum Ratings" corrected footnote on clamp of
TEST pin.
Added cycle definition to "CPU 12 Block Description".
Added register reset values to MMC and MEBI block descriptions.
Diagram "Clock Connections": Connect Bus Clock to HCS12 Core
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