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MC9S12P32CFT Datasheet, PDF (499/566 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers | |||
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Timer Module (TIM16B8CV2) Block Description
The pulse accumulator counter register reï¬ect the number of pulses from the divided-by-64 clock since the
last reset.
NOTE
The timer prescaler generates the divided-by-64 clock. If the timer is not
active, there is no divided-by-64 clock.
14.5 Resets
The reset state of each individual bit is listed within Section 14.3, âMemory Map and Register Deï¬nitionâ
which details the registers and their bit ï¬elds.
14.6 Interrupts
This section describes interrupts originated by the TIM16B8CV2 block. Table 14-24 lists the interrupts
generated by the TIM16B8CV2 to communicate with the MCU.
Table 14-24. TIM16B8CV1 Interrupts
Interrupt
Offset
(1)
Vector1
Priority1
Source
Description
C[7:0]F
â
â
PAOVI
â
â
â
Timer Channel 7â0
Active high timer channel interrupts 7â0
â
Pulse Accumulator Active high pulse accumulator input interrupt
Input
PAOVF
â
â
â
Pulse Accumulator
Overï¬ow
Pulse accumulator overï¬ow interrupt
TOF
â
â
â
Timer Overï¬ow
1. Chip Dependent.
Timer Overï¬ow interrupt
The TIM16B8CV2 uses a total of 11 interrupt vectors. The interrupt vector offsets and interrupt numbers
are chip dependent.
14.6.1 Channel [7:0] Interrupt (C[7:0]F)
This active high outputs will be asserted by the module to request a timer channel 7 â 0 interrupt to be
serviced by the system controller.
14.6.2 Pulse Accumulator Input Interrupt (PAOVI)
This active high output will be asserted by the module to request a timer pulse accumulator input interrupt
to be serviced by the system controller.
14.6.3 Pulse Accumulator Overï¬ow Interrupt (PAOVF)
This active high output will be asserted by the module to request a timer pulse accumulator overï¬ow
interrupt to be serviced by the system controller.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
499
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