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MC9S12P32CFT Datasheet, PDF (274/566 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers | |||
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Freescaleâs Scalable Controller Area Network (S12MSCANV3)
Table 8-23. CANIDAR4âCANIDAR7 Register Field Descriptions
Field
7-0
AC[7:0]
Description
Acceptance Code Bits â AC[7:0] comprise a user-deï¬ned sequence of bits with which the corresponding bits
of the related identiï¬er register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identiï¬er mask register.
8.3.2.18 MSCAN Identiï¬er Mask Registers (CANIDMR0âCANIDMR7)
The identiï¬er mask register speciï¬es which of the corresponding bits in the identiï¬er acceptance register
are relevant for acceptance ï¬ltering. To receive standard identiï¬ers in 32 bit ï¬lter mode, it is required to
program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to âdonât care.â
To receive standard identiï¬ers in 16 bit ï¬lter mode, it is required to program the last three bits (AM[2:0])
in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to âdonât care.â
Module Base + 0x0014 to Module Base + 0x0017
R
W
Reset
7
AM7
0
6
AM6
0
5
AM5
0
4
AM4
0
3
AM3
0
2
AM2
0
Access: User read/write(1)
1
0
AM1
AM0
0
0
Figure 8-22. MSCAN Identiï¬er Mask Registers (First Bank) â CANIDMR0âCANIDMR3
1. Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 8-24. CANIDMR0âCANIDMR3 Register Field Descriptions
Field
7-0
AM[7:0]
Description
Acceptance Mask Bits â If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identiï¬er acceptance register must be the same as its identiï¬er bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identiï¬er
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identiï¬er bits
1 Ignore corresponding acceptance code register bit
Module Base + 0x001C to Module Base + 0x001F
R
W
Reset
7
AM7
0
6
AM6
0
5
AM5
0
4
AM4
0
3
AM3
0
2
AM2
0
Access: User read/write(1)
1
0
AM1
AM0
0
0
Figure 8-23. MSCAN Identiï¬er Mask Registers (Second Bank) â CANIDMR4âCANIDMR7
S12P-Family Reference Manual, Rev. 1.13
274
Freescale Semiconductor
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