MC9S12P32CFT Datasheet, PDF (482/566 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Timer Module (TIM16B8CV2) Block Description
14.3.2.4 Output Compare 7 Data Register (OC7D)
Module Base + 0x0003
R
W
Reset
7
OC7D7
0
Read: Anytime
Write: Anytime
6
OC7D6
5
OC7D5
4
OC7D4
3
OC7D3
2
OC7D2
0
0
0
0
0
Figure 14-9. Output Compare 7 Data Register (OC7D)
1
OC7D1
0
0
OC7D0
0
Table 14-5. OC7D Field Descriptions
Field
Description
7:0
Output Compare 7 Data — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a
OC7D[7:0] successful output compare on channel 7, can cause bits in the output compare 7 data register to transfer to the
timer port data register depending on the output compare 7 mask register.
14.3.2.5 Timer Count Register (TCNT)
Module Base + 0x0004
R
W
Reset
15
TCNT15
0
14
TCNT14
13
TCNT13
12
TCNT12
11
TCNT11
10
TCNT10
0
0
0
0
0
Figure 14-10. Timer Count Register High (TCNTH)
9
TCNT9
0
9
TCNT8
0
Module Base + 0x0005
7
R
TCNT7
W
6
TCNT6
5
TCNT5
4
TCNT4
3
TCNT3
2
TCNT2
1
TCNT1
0
TCNT0
Reset
0
0
0
0
0
0
0
0
Figure 14-11. Timer Count Register Low (TCNTL)
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give a different result than accessing them as a word.
Read: Anytime
S12P-Family Reference Manual, Rev. 1.13
482
Freescale Semiconductor