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MC9S12P32CFT Datasheet, PDF (156/566 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers | |||
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S12S Debug Module (S12SDBGV2)
6.1.2 Overview
The comparators monitor the bus activity of the CPU module. A match can initiate a state sequencer
transition. On a transition to the Final State, bus tracing is triggered and/or a breakpoint can be generated.
Independent of comparator matches a transition to Final State with associated tracing and breakpoint can
be triggered immediately by writing to the TRIG control bit.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads. Tracing is disabled when the MCU system is secured.
6.1.3 Features
⢠Three comparators (A, B and C)
â Comparators A compares the full address bus and full 16-bit data bus
â Comparator A features a data bus mask register
â Comparators B and C compare the full address bus only
â Each comparator features selection of read or write access cycles
â Comparator B allows selection of byte or word access cycles
â Comparator matches can initiate state sequencer transitions
⢠Three comparator modes
â Simple address/data comparator match mode
â Inside address range mode, Addmin ⤠Address ⤠Addmax
â Outside address range match mode, Address < Addmin or Address > Addmax
⢠Two types of matches
â Tagged â This matches just before a speciï¬c instruction begins execution
â Force â This is valid on the ï¬rst instruction boundary after a match occurs
⢠Two types of breakpoints
â CPU breakpoint entering BDM on breakpoint (BDM)
â CPU breakpoint executing SWI on breakpoint (SWI)
⢠Trigger mode independent of comparators
â TRIG Immediate software trigger
⢠Four trace modes
â Normal: change of ï¬ow (COF) PC information is stored (see 6.4.5.2.1) for change of ï¬ow
deï¬nition.
â Loop1: same as Normal but inhibits consecutive duplicate source address entries
â Detail: address and data for all cycles except free cycles and opcode fetches are stored
â Compressed Pure PC: all program counter addresses are stored
⢠4-stage state sequencer for trace buffer control
â Tracing session trigger linked to Final State of state sequencer
â Begin and End alignment of tracing to trigger
S12P-Family Reference Manual, Rev. 1.13
156
Freescale Semiconductor
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