908E621_08 Datasheet, PDF (49/65 Pages) Freescale Semiconductor, Inc – Integrated Quad Half-bridge and Triple High Side with Embedded MCU and LIN for High End Mirror

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SPI REGISTER OVERVIEW
TABLE 12 SUMMARIZES THE SPI REGISTER ADDRESSES AND THE BIT NAMES OF EACH REGISTER.
Table 12. SPI Register Overview
Bit
Addr
Register Name
R/W
7
6
5
4
3
2
1
0
System Control
R
0
0
$00
(SYSCTL)
PSON
HTIS1
HTIS0
VIS
W
STOP
SLEEP
SRS1
SRS0
Half-bridge Output
R
$01
(HBOUT)
HB4_H
W
HB4_L HB3_H
HB3_L
HB2_H
HB2_L
HB1_H
HB1_L
High Side Output
R
$02
(HSOUT)
HVDDON
W
0
HS3PWM HS2PWM HS1PWM HS3ON HS2ON HS1ON
Half-bridge Status and ^R
0
0
0
$03
Control (HBSCTL)
W
CRM
HB4OCF HB3OCF HB2OCF HB1OCF
High Side Status and ^R
0
0
0
0
$04
Control (HSSCTL)
HVDDOCF
W
HS3OCF HS2OCF HS1OCF
R
$05
Reserved
W
reserved
R
$06
Reserved
W
reserved
H0/L0 Status and
R
L0F
0
$07
Control (HLSCTL)
W
0
H0F
H0OCF
H0EN
H0PD
H0MS
A0 and Multiplexer
R
$08 _{Control (A0MUCTL)}
CSON CSSEL1 CSSEL0
CSA
SS3
SS2
SS1
SS0
W
Interrupt Mask
R
$09
(IMR)
L0IE
W
H0IE
LINIE
HTRD
HTIE
LVIE
HVIE
PSFIE
Interrupt Flag
R
PSFIF
$0A
(IFR)
L0IF
H0IF
LINIF
0
HTIF
LVIF
HVIF
W
Watchdog Control
R
$0B
(WDCTL)
WDRE
W
System Status
R
LINCL
$0C
(SYSSTAT)
W
WDP1
HTIF
WDP0
VF
0
0
0
H0F
HVDDF
HSF
0
HBF
0
WDRST
0
Reset Status
R
$0D
(RSR)
POR
PINR
WDR
HTR
LVR
W
0
LINWF
L0WF
System Test
R
$0E
(SYSTEST)
W
reserved
System Trim 1
R
$0F
(SYSTRIM1)
HVDDT1 HVDDT0 reserved reserved
W
itrim3
itrim2
itrim1
itrim0
System Trim 2
R
0
0
0
0
0
0
0
0
$10
(SYSTRIM2)
W _{CRHBHC1 CRHBHC0 CRHB5}
CRHB4
CRHB3
CRHB2
CRHB1
CRHB0
$11
System Trim 3
(SYSTRIM3)
R
0
0
0
W _{CRHBHC3 CRHBHC2 CRHS5}
0
CRHS4
0
CRHS3
0
CRHS2
0
CRHS1
0
CRHS0
Analog Integrated Circuit Device Data
Freescale Semiconductor
908E621
49