F75111 Datasheet, PDF (36/45 Pages) Feature Integration Technology Inc. – Low Power GPIO Datasheet

7.46 GPIO3x Pulse Inverse Register – Index 47h
F75111
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-4 Reserved
RO
VSB3V Read back will be zero
3
GP33_PULSINV R/W
VSB3V GPIO33 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR44.
2
GP32_PULSINV R/W
VSB3V GPIO32 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR44.
1
GP31_PULSINV R/W
VSB3V GPIO 31 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR44.
0
GP30_PULSINV R/W
VSB3V GPIO30 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR44.
7.47 GP3x Edge Detector Enable Register – Index 0x48
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-4 Reserved
RO VSB3V Read back will be zero
3
EN_GP33EDGE R/W VSB3V Enable GPIO33 Edge Detector. If set to 1, enable GPIO33 edge
detection. Default is disable.
2
EN_GP32EDGE R/W VSB3V Enable GPIO32 Edge Detector. If set to 1, enable GPIO32 edge
detection. Default is disable.
1
EN_GP31EDGE R/W VSB3V Enable GPIO31 Edge Detector. If set to 1, enable GPIO31 edge
detection. Default is disable.
0
EN_GP30EDGE R/W VSB3V Enable GPIO30 Edge Detector. If set to 1, enable GPIO30 edge
detection. Default is disable.
7.48 GP3X Edge Detector Status Register – Index 0x49
Power-on default [7:0] =0000_0000b
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July, 2007
V0.27P