F75111 Datasheet, PDF (33/45 Pages) Feature Integration Technology Inc. – Low Power GPIO Datasheet

6-0 WD1_PTIME
R/W VSB3V
WDTOUT10 Pre-counter time in second.
000_0000b – 0 second (Default)
000_0001b – 1 second
000_0010b – 2 seconds
:
111_1111b – 127 seconds
F75111
7.38 Watchdog Timer Control Register – Index 36h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7
Reserved
RO VSB3V Reserved. Read will return 0.
6
STS_WD_TMO R/W VSB3V Watchdog is timeout. When the watchdog is timeout, this bit will be set to
UT
one. If set to 1, write 1 will clear this bit. Write 0, no effect.
5
WD_ENABLE R/W VSB3V Enable watchdog timer.
4
WD_PULSE
R/W VSB3V Watchdog output level or pulse. If set 0 (default), the pin of watchdog is
level output. If write 1, the pin will output with a pulse.
3
WD_UNIT
R/W VSB3V Watchdog unit select. Default 0 is select second. Write 1 to select minute.
2
WD_HACTIVE R/W VSB3V Program WD2 output level. If set to 1 and watchdog asserted, the pin will
be high. If set to 0 and watchdog asserted, this pin will drive low(default).
1-0 WD_PSWIDTH R/W VSB3V Watchdog pulse width selection. If the pin output is selected to pulse
mode. The pulse width can be choice.
00b – 1m second.
01b – 20m second.
10b – 100m second
11b – 4 second
The is flexible reset out with watchdog
7.39 Watchdog Timer Range Register – Index 37h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-0
WD_TIME R/W VSB3V Watchdog timing range from 0 ~ 255. The unit is either second or minute
programmed by the watchdog timer control register bit3.
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July, 2007
V0.27P